TMS320TCI6482GTZ Datasheet, PDF (191/260 Pages) Texas Instruments – Communications Infrastructure Digital Signal Processor

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HEX ADDRESS RANGE
0290 0000
3400 0000
0290 0004
3400 0010
0290 0008
0290 000C
0290 0010
0290 0014
0290 0018
0290 001C
0290 0020
0290 0024
0290 0028
0290 002C
0290 0030
0290 0034
0290 0038
0290 003C
0290 0040 - 0293 FFFF
TMS320TCI6482
SPRS246K – APRIL 2005 – REVISED MARCH 2012
Table 8-58. McBSP 1 Registers
ACRONYM
DRR1
DRR1
DXR1
DXR1
SPCR1
RCR1
XCR1
SRGR1
MCR1
RCERE01
XCERE01
PCR1
RCERE11
XCERE11
RCERE21
XCERE21
RCERE31
XCERE31
-
REGISTER NAME
McBSP1 Data Receive Register via Configuration Bus
McBSP1 Data Receive Register via EDMA bus
McBSP1 Data Transmit Register via configuration bus
McBSP1 Data Transmit Register via EDMA bus
McBSP1 serial port control register
McBSP1 Receive Control Register
McBSP1 Transmit Control Register
McBSP1 sample rate generator register
McBSP1 multichannel control register
McBSP1 Enhanced Receive Channel Enable
Register 0 Partition A/B
McBSP1 Enhanced Transmit Channel Enable
Register 0 Partition A/B
McBSP1 Pin Control Register
McBSP1 Enhanced Receive Channel Enable
Register 1 Partition C/D
McBSP1 Enhanced Transmit Channel Enable
Register 1 Partition C/D
McBSP1 Enhanced Receive Channel Enable
Register 2 Partition E/F
McBSP1 Enhanced Transmit Channel Enable
Register 2 Partition E/F
McBSP1 Enhanced Receive Channel Enable
Register 3 Partition G/H
McBSP1 Enhanced Transmit Channel Enable
Register 3 Partition G/H
Reserved
COMMENTS
The CPU and EDMA
controller can only read
this register; they cannot
write to it.
Copyright © 2005–2012, Texas Instruments Incorporated
C64x+ Peripheral Information and Electrical Specifications 191
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