TMS320TCI6482GTZ Datasheet, PDF (211/260 Pages) Texas Instruments – Communications Infrastructure Digital Signal Processor

TMS320TCI6482
www.ti.com
8.14.3 EMAC Electrical Data/Timing
8.14.3.1 EMAC MII and GMII Electrical Data/Timing
SPRS246K – APRIL 2005 – REVISED MARCH 2012
(see Figure 8-59)
NO.
1
t_c(MRCLK)
2
t_w(MRCLKH)
3
t_w(MRCLKL)
4
t_t(MRCLK)
Table 8-75. Timing Requirements for MRCLK - MII and GMII Operation
Cycle time, MRCLK
Pulse duration, MRCLK high
Pulse duration, MRCLK low
Transition time, MRCLK
1000 Mbps
(GMII Only)
MIN MAX
8
2.8
2.8
1
-850
A-1000/-1000
-1200
100 Mbps
MIN MAX
40
14
14
3
10 Mbps
UNIT
MIN MAX
400
ns
140
ns
140
ns
3 ns
1
2
4
3
4
MRCLK
(Input)
Figure 8-59. MRCLK Timing (EMAC - Receive) [MII and GMII Operation]
(see Figure 8-60)
NO.
1
t_c(MTCLK)
2
t_w(MTCLKH)
3
t_w(MTCLKL)
4
t_t(MTCLK)
Table 8-76. Timing Requirements for MTCLK - MII and GMII Operation
Cycle time, MTCLK
Pulse duration, MTCLK high
Pulse duration, MTCLK low
Transition time, MTCLK
-850
A-1000/-1000
-1200
100 Mbps
10 Mbps
MIN
MAX
MIN
MAX
40
400
14
140
14
140
3
3
UNIT
ns
ns
ns
ns
1
2
4
4
3
MTCLK
(Input)
Figure 8-60. MTCLK Timing (EMAC - Transmit) [MII and GMII Operation]
Copyright © 2005–2012, Texas Instruments Incorporated
C64x+ Peripheral Information and Electrical Specifications 211
Submit Documentation Feedback
Product Folder Link(s): TMS320TCI6482