TMS320TCI6482GTZ Datasheet, PDF (170/260 Pages) Texas Instruments – Communications Infrastructure Digital Signal Processor

TMS320TCI6482
SPRS246K – APRIL 2005 – REVISED MARCH 2012
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AECLKOUT
ACEx
ABE[7:0]
AEA[19:0]/ABA[1:0]
AED[63:0]
ASADS/ASRE ^(B)
Write
Latency =
1 ^(B)
1
2
BE1
4
EA1
10
8
BE2
EA2
10
Q1
BE3
EA3
Q2
1
3
BE4
5
EA4
11
Q3
Q4
8
AAOE/ASOE ^(B)
12
12
AAWE/ASWE ^(B)
A The following parameters are programmable via the EMIFA Chip Select n Configuration Register (CESECn):
− Read latency (R_LTNCY): 1-, 2-, or 3-cycle read latency
− Write latency (W_LTNCY): 0-, 1-, 2-, or 3-cycle write latency
− ACEx assertion length (CE_EXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been
issued (CE_EXT = 0). For synchronous FIFO interface, ACEx is active when ASOE is active (CE_EXT = 1).
− Function of ASADS/ASRE (R_ENABLE): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect
cycles (R_ENABLE = 0). For FIFO interface, ASADS/ASRE acts as SRE with NO deselect cycles (R_ENABLE = 1).
− In this figure W_LTNCY = 1, CE_EXT = 0, R_ENABLE = 0, and SSEL = 1.
B AAOE/ASOE, and AAWE/ASWE operate as ASOE, and ASWE, respectively, during programmable synchronous interface accesses.
Figure 8-38. Programmable Synchronous Interface Write Timing for EMIFA (With Write Latency = 1) ^(A)
170 C64x+ Peripheral Information and Electrical Specifications
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