TMS320TCI6482GTZ Datasheet, PDF (208/260 Pages) Texas Instruments – Communications Infrastructure Digital Signal Processor

TMS320TCI6482
SPRS246K – APRIL 2005 – REVISED MARCH 2012
www.ti.com
Table 8-71. Ethernet MAC (EMAC) Control Registers (continued)
HEX ADDRESS RANGE
02C8 0158
02C8 015C
02C8 0160
02C8 0164
02C8 0168
02C8 016C
02C8 0170
02C8 0174
02C8 0178 - 02C8 01CC
02C8 01D0
02C8 01D4
02C8 01D8
02C8 01DC
02C8 01E0
02C8 01E4
02C8 01E8
02C8 01EC
02C8 01F0 - 02C8 01FC
02C8 0200 - 02C8 02FC
02C8 0300 - 02C8 03FC
02C8 0400 - 02C8 04FC
02C8 0500
02C8 0504
02C8 0508
02C8 050C - 02C8 05FC
02C8 0600
02C8 0604
02C8 0608
02C8 060C
02C8 0610
02C8 0614
02C8 0618
02C8 061C
02C8 0620
02C8 0624
02C8 0628
02C8 062C
02C8 0630
02C8 0634
02C8 0638
02C8 063C
02C8 0640
02C8 0644
02C8 0648
ACRONYM
RX6FREEBUFFER
RX7FREEBUFFER
MACCONTROL
MACSTATUS
EMCONTROL
FIFOCONTROL
MACCONFIG
SOFTRESET
-
MACSRCADDRLO
MACSRCADDRHI
MACHASH1
MACHASH2
BOFFTEST
TPACETEST
RXPAUSE
TXPAUSE
-
(see Table 8-72)
-
-
MACADDRLO
MACADDRHI
MACINDEX
-
TX0HDP
TX1HDP
TX2HDP
TX3HDP
TX4HDP
TX5HDP
TX6HDP
TX7HDP
RX0HDP
RX1HDP
RX2HDP
RX3HDP
RX4HDP
RX5HDP
RX6HDP
RX7HDP
TX0CP
TX1CP
TX2CP
REGISTER NAME
Receive Channel 6 Free Buffer Count Register
Receive Channel 7 Free Buffer Count Register
MAC Control Register
MAC Status Register
Emulation Control Register
FIFO Control Register (Transmit and Receive)
MAC Configuration Register
Soft Reset Register
Reserved
MAC Source Address Low Bytes Register (Lower 32-bits)
MAC Source Address High Bytes Register (Upper 32-bits)
MAC Hash Address Register 1
MAC Hash Address Register 2
Back Off Test Register
Transmit Pacing Algorithm Test Register
Receive Pause Timer Register
Transmit Pause Timer Register
Reserved
EMAC Statistics Registers
Reserved
Reserved
MAC Address Low Bytes Register (used in receive address
matching)
MAC Address High Bytes Register (used in receive address
matching)
MAC Index Register
Reserved
Transmit Channel 0 DMA Head Descriptor Pointer Register
Transmit Channel 1 DMA Head Descriptor Pointer Register
Transmit Channel 2 DMA Head Descriptor Pointer Register
Transmit Channel 3 DMA Head Descriptor Pointer Register
Transmit Channel 4 DMA Head Descriptor Pointer Register
Transmit Channel 5 DMA Head Descriptor Pointer Register
Transmit Channel 6 DMA Head Descriptor Pointer Register
Transmit Channel 7 DMA Head Descriptor Pointer Register
Receive Channel 0 DMA Head Descriptor Pointer Register
Receive Channel 1 DMA Head Descriptor Pointer Register
Receive Channel 2 DMA Head Descriptor Pointer Register
Receive Channel 3 DMA Head Descriptor Pointer Register
Receive Channel 4 DMA Head Descriptor Pointer Register
Receive Channel 5 DMA Head Descriptor Pointer Register
Receive Channel 6 DMA Head Descriptor Pointer Register
Receive Channel 7 DMA Head Descriptor Pointer Register
Transmit Channel 0 Completion Pointer (Interrupt Acknowledge)
Register
Transmit Channel 1 Completion Pointer (Interrupt Acknowledge)
Register
Transmit Channel 2 Completion Pointer (Interrupt Acknowledge)
Register
208 C64x+ Peripheral Information and Electrical Specifications
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