TMS320TCI6482GTZ Datasheet, PDF (166/260 Pages) Texas Instruments – Communications Infrastructure Digital Signal Processor

TMS320TCI6482
SPRS246K – APRIL 2005 – REVISED MARCH 2012
www.ti.com
Table 8-45. Switching Characteristics Over Recommended Operating Conditions for Asynchronous
Memory Cycles for EMIFA Module^{(1) (2) (3)}
(see Figure 8-33 and Figure 8-34)
NO.
PARAMETER
-850
A-1000/-1000
-1200
UNIT
MIN
MAX
1
t_{osu(SELV-AOEL)}
2
t_{oh(AOEH-SELIV)}
10
t_d(EKOH-AOEV)
11
t_{osu(SELV-AWEL)}
12
t_{oh(AWEH-SELIV)}
13
t_d(EKOH-AWEV)
Output setup time, select signals valid to AAOE low
Output hold time, AAOE high to select signals invalid
Delay time, AECLKOUT high to AAOE valid
Output setup time, select signals valid to AAWE low
Output hold time, AAWE high to select signals invalid
Delay time, AECLKOUT high to AAWE valid
RS * E - 1.5
RS * E - 1.9
1
WS * E - 1.7
WH * E - 1.8
1.3
ns
ns
7 ns
ns
ns
7.1 ns
(1) E = AECLKOUT period in ns for EMIFA
(2) RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters
are programmed via the EMIFA CE Configuration registers (CEnCFG).
(3) Select signals for EMIFA include: ACEx, ABE[7:0], AEA[19:0], ABA[1:0]; and for EMIFA writes, also include AR/W, AED[63:0].
AECLKOUT
ACEx
ABE[7:0]
AEA[19:0]/
ABA[1:0]
AED[63:0]
AAOE/ASOE^(A)
Setup = 1
1
1
1
10
Strobe = 4
Byte Enables
Address
Hold = 1
2
2
2
3
4
Read Data
10
AAWE/ASWE^(A)
AR/W
AARDY^(B)
DEASSERTED
A AAOE/ASOE and AAWE/ASWE operate as AAOE (identified under select signals) and AAWE, respectively, during asynchronous
memory accesses.
B Polarity of the AARDY signal is programmable through the AP field of the EMIFA Async Wait Cycle Configuration register (AWCC).
Figure 8-33. Asynchronous Memory Read Timing for EMIFA
166 C64x+ Peripheral Information and Electrical Specifications
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