TLC1542_13 Datasheet, PDF (8/33 Pages) Texas Instruments – 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS

TLC1542I, TLC1542M, TLC1542Q
TLC1542C, TLC1543C, TLC1543I, TLC1543Q
SLAS052G – MARCH 1992 – REVISED JANUARY 2006
www.ti.com
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)⁽¹⁾
V_CC, see ⁽²⁾
V_I
V_O
V_ref+
V_ref-
T_A
T_stg
Supply voltage range
Input voltage range
Output voltage range
Positive reference voltage
Negative reference voltage
Peak input current (any input)
Peak total input current (all inputs)
TLC1542C, TLC1543C
Operating free-air temperature range
TLC1542I, TLC1543I
TLC1542Q, TLC1543Q
TLC1542M
Storage temperature range,
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds
UNIT
-0.5 V to 6.5 V
-0.3 V to V_CC + 0.3 V
-0.3 V to V_CC + 0.3 V
V_CC + 0.1 V
-0.1 V
±20 mA
±30 mA
0°C to 70°C
-40°C to 85°C
-40°C to 125°C
-55°C to 125°C
-65°C to 150°C
260°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to digital ground with REF- and GND wired together (unless otherwise noted).
RECOMMENDED OPERATING CONDITIONS
V_CC
V_ref+, see ⁽¹⁾
V_ref-, see ⁽¹⁾
V_ref+-V_ref-, see ⁽¹⁾
V_IH
V_IL
t_su(A), see Figure 4
t_h(A), see Figure 4
t_h(CS), see Figure 5
t_su(CS), see ⁽²⁾ and
Figure 5
t_wH(I/O)
t_wL(I/O)
t_t(I/O), see ⁽⁴⁾ and
Figure 6
t_t(CS)
Supply voltage
Positive reference voltage
Negative reference voltage
Differential reference voltage
Analog input voltage ,see ⁽¹⁾
High-level control input voltage
Low-level control input voltage
Setup time, address bits at data input before I/O
CLOCK↑
Hold time, address bits after I/O CLOCK↑
Hold time, CS low after last I/O CLOCK↓
Setup time, CS low before clocking in first
address bit
Clock frequency at I/O CLOCK, see ⁽³⁾
Pulse duration, I/O CLOCK high,
Pulse duration, I/O CLOCK low,
V_CC = 4.5 V to 5.5 V
V_CC = 4.5 V to 5.5 V
Transition time, I/O CLOCK,
Transition time, ADDRESS and CS,
MIN
4.5
2.5
0
2
100
0
0
1.425
0
190
190
NOM MAX
5
5.5
V_CC
0
V_CC
V_CC+0.
2
V_CC
0.8
2.1
1
10
UNIT
V
V
V
V
V
V
V
ns
ns
ns
µs
MHz
ns
ns
µs
µs
(1) Analog input voltages greater than that applied to REF+ convert as all ones (1111111111), while input voltages less than that applied to
REF- convert as all zeros (0000000000). The device is functional with reference voltages down to 1 V (V_ref+ - V_ref-); however, the
electrical specifications are no longer applicable.
(2) To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system clock
after CS↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS
setup time has elapsed.
(3) For 11- to 16-bit transfers, after the tenth I/O CLOCK falling edge (≤ 2 V) at least 1 I/O CLOCK rising edge (≥ 2 V) must occur within 9.5
µs.
(4) This is the time required for the clock input signal to fall from V_IHmin to V_ILmax or to rise from V_ILmax to V_IHmin. In the vicinity of normal
room temperature, the devices function with input clock transition time as slow as 1 µs for remote data-acquisition applications where
the sensor and the A/D converter are placed several feet away from the controlling microprocessor.
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