TLC1542_13 Datasheet, PDF (6/33 Pages) Texas Instruments – 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS

TLC1542I, TLC1542M, TLC1542Q
TLC1542C, TLC1543C, TLC1543I, TLC1543Q
SLAS052G – MARCH 1992 – REVISED JANUARY 2006
Table 2. ANALOG-CHANNEL-SELECT ADDRESS
ANALOG INPUT SELECTED
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
VALUE SHIFTED INTO ADDRESS
INPUT
BINARY
HEX
0000
0
0001
1
0010
2
0011
3
0100
4
0101
5
0110
6
0111
7
1000
8
1001
9
1010
A
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Table 3. TEST-MODE-SELECT ADDRESS
INTERNAL SELF-TEST
VOLTAGE SELECTED⁽¹⁾
VALUE SHIFTED INTO
ADDRESS INPUT
BINARY
HEX
OUTPUT RESULT (HEX)⁽²⁾
V_ref+ − V_ref−
1011
B
200
2
V_ref-
1100
C
000
V_ref+
1101
D
3FF
(1) V_ref+ is the voltage applied to the REF+ input, and V_ref- is the voltage applied to the REF- input.
(2) The output results shown are the ideal values and vary with the reference stability and with internal
offsets.
CONVERTER AND ANALOG INPUT
The CMOS threshold detector in the successive-approximation conversion system determines each bit by
examining the charge on a series of binary-weighted capacitors (see Figure 1). In the first phase of the
conversion process, the analog input is sampled by closing the S_C switch and all S_T switches simultaneously.
This action charges all the capacitors to the input voltage.
In the next phase of the conversion process, all S_T and S_C switches are opened and the threshold detector
begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference (REF-)
voltage. In the switching sequence, ten capacitors are examined separately until all ten bits are identified and
then the charge-convert sequence is repeated. In the first step of the conversion phase, the threshold detector
looks at the first capacitor (weight = 512). Node 512 of this capacitor is switched to the REF+ voltage, and the
equivalent nodes of all the other capacitors on the ladder are switched to REF-. If the voltage at the summing
node is greater than the trip point of the threshold detector (approximately one-half V_CC), a 0 bit is placed in the
output register and the 512-weight capacitor is switched to REF-. If the voltage at the summing node is less than
the trip point of the threshold detector, a 1 bit is placed in the register and the 512-weight capacitor remains
connected to REF+ through the remainder of the successive-approximation process. The process is repeated for
the 256-weight capacitor, the 128-weight capacitor, and so forth down the line until all bits are counted.
With each step of the successive-approximation process, the initial charge is redistributed among the capacitors.
The conversion process relies on charge redistribution to count and weigh the bits from MSB to LSB.
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