TLC1542_13 Datasheet, PDF (10/33 Pages) Texas Instruments – 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS

TLC1542I, TLC1542M, TLC1542Q
TLC1542C, TLC1543C, TLC1543I, TLC1543Q
SLAS052G – MARCH 1992 – REVISED JANUARY 2006
www.ti.com
OPERATING CHARACTERISTICS (continued)
over recommended operating free-air temperature range, V_CC = V_ref+ = 4.5 V to 5.5 V, I/O CLOCK frequency = 2.1 MHz
(unless otherwise noted)
E_ZS
E_FS
t_conv
t_c
t_acq
t_v
t_d(I/O-DATA)
t_d(I/O-EOC)
t_d(EOC-DATA)
t_PZH, t_PZL
t_PHZ, t_PLZ
t_r(EOC)
t_f(EOC)
t_r(DATA)
t_f(DATA)
t_d(I/O-CS)
Zero-scale error, see ⁽³⁾
Full-scale error, see ⁽³⁾
Total unadjusted error, see ⁽⁵⁾
TLC1542C, I, or Q
TLC1543C, I, or Q
TLC1542M
TLC1542C, I, or Q
TLC1543C, I, or Q
TLC1542M
TLC1542C, I, or Q
TLC1543C, I, or Q
TLC1542M
Self-test output code, see Table 3 and ⁽⁶⁾
Conversion time
TEST
CONDITIONS
See ⁽⁴⁾
See ⁽⁴⁾
See ⁽⁴⁾
See ⁽⁴⁾
See ⁽⁴⁾
See ⁽⁴⁾
ADDRESS = 1011
ADDRESS = 1100
ADDRESS = 1101
See timing
diagrams
Total cycle time (access, sample, and conversion)
See timing
diagrams and ⁽⁷⁾
Channel acquisition time (sample)
Valid time, DATA OUT remains valid after I/O CLOCK↓
Delay time, I/O CLOCK↓ to DATA OUT valid
Delay time, tenth I/O CLOCK↓ to EOC↓
Delay time, EOC↑ to DATA OUT (MSB)
Enable time, CS↓ to DATA OUT (MSB driven)
Disable time, CS↑ to DATA OUT (high impedance)
Rise time, EOC
Fall time, EOC
Rise time, data bus
Fall time, data bus
Delay time, tenth I/O CLOCK↓ to CS↓ to abort
conversion (see Note ⁽⁸⁾)
See timing
diagrams and ⁽⁷⁾
See Figure 6
See Figure 6
See Figure 7
See Figure 8
See Figure 3
See Figure 3
See Figure 8
See Figure 7
See Figure 6
See Figure 6
MIN TYP ⁽¹⁾
MAX UNIT
512
0
1023
±1
LSB
±1
LSB
±1
LSB
±1
LSB
±1
LSB
±1
LSB
±1
LSB
±1
LSB
±1
LSB
21
µs
21
+10 I/O
CLOCK
µs
periods
6
I/O CLOCK
periods
10
ns
240
ns
70
240
ns
100
ns
1.3
µs
150
ns
300
ns
300
ns
300
ns
300
ns
9
µs
(3) Zero-scale error is the difference between 0000000000 and the converted output for zero input voltage; full-scale error is the difference
between 1111111111 and the converted output for full-scale input voltage.
(4) Analog input voltages greater than that applied to REF+ convert as all ones (1111111111), while input voltages less than that applied to
REF- convert as all zeros (0000000000). The device is functional with reference voltages down to 1 V (V_ref+-V_ref-); however, the
electrical specifications are no longer applicable.
(5) Total unadjusted error comprises linearity, zero-scale, and full-scale errors.
(6) Both the input address and the output codes are expressed in positive logic.
(7) I/O CLOCK period = 1/(I/O CLOCK frequency) (see Figure 6)
(8) Any transitions of CS are recognized as valid only if the level is maintained for a setup time plus two falling edges of the internal clock
(1.425 µs) after the transition.
10
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