TLC1542_13 Datasheet, PDF (16/33 Pages) Texas Instruments – 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS

TLC1542I, TLC1542M, TLC1542Q
TLC1542C, TLC1543C, TLC1543I, TLC1543Q
www.ti.com
SLAS052G – MARCH 1992 – REVISED JANUARY 2006
PARAMETER MEASUREMENT INFORMATION (continued)
ÏÏÏÏÏÏ _CS
ÏÏÏÎÎ _{(see Note A)}
ÏÏÏÎÎÎÎ _I/O
1
2
3
4
5
6
7
8
9
10
11
16
1
CLOCK
ÎÎ _{Access Cycle B}
Sample Cycle B
See Note B
ÎÎÎÎÎÎ DATA
OUT
Low ^{Hi-Z State}
A9
A8 A7 A6 A5 A4 A3 A2 A1 A0
Level
B9
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ _MSB
Previous Conversion Data
LSB
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ _ADDRESS
ÎÎÎÎÎÎÎÎÎÎÎ ÏÏÏ ÎÎÎÎ _{B3 B2 B1 B0}
C3
MSB
LSB
ÏÏÏÏÏÏÏÏÏ _EOC
Shift in New Multiplexer Address;
Simultaneously Shift Out Previous
Conversion Value
A/D Conversion
Initialize
Interval
Initialize
A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the
internal system clock after CS↓ before responding to control input signals. Therefore, no attempt should be made to
clock in an address until the minimum CS setup time has elapsed.
B. The 11th rising edge of the I/O CLOCK sequence must occur before the conversion is complete to prevent losing
serial interface synchronization.
Figure 13. Timing for 11- to 16-Clock Transfer Using
CS (Serial Transfer Interval Longer Than Conversion)
16
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