TLC1542_13 Datasheet, PDF (14/33 Pages) Texas Instruments – 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS

TLC1542I, TLC1542M, TLC1542Q
TLC1542C, TLC1543C, TLC1543I, TLC1543Q
www.ti.com
SLAS052G – MARCH 1992 – REVISED JANUARY 2006
PARAMETER MEASUREMENT INFORMATION (continued)
ÏÏÏÏÏÏ _{See Note B}
ÏÏÏÎÎÎ _CS
ÏÏÏÎÎÎ ^{(see Note A)}
ÎÎÎ I/O
1
2
3
4
5
6
7
8
9
10
11 16
1
CLOCK
ÎÎÎ _{Access Cycle B}
Sample Cycle B
ÎÎÎ _Low
ÎÎÎ ^DATA
A9
A8 A7
A6 A5
A4
A3 A2
A1
A0 ^Level
Hi-Z
B9
OUT
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ _MSB
Previous Conversion Data
LSB
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ _ADDRESS
B3
B2
B1 B0
C3
MSB
LSB
EOC
Initialize
Shift in New Multiplexer Address;
Simultaneously Shift Out Previous
Conversion Value
A/D Conversion
Interval
Initialize
A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the
internal system clock after CS↓ before responding to control input signals. Therefore, no attempt should be made to
clock in an address until the minimum CS setup time has elapsed.
B. A low-to-high transition of CS disables ADDRESS and the I/O CLOCK within a maximum of a setup time plus two
falling edges of the internal system clock.
Figure 11. Timing for 11- to 16-Clock Transfer Using
CS (Serial Transfer Interval Shorter Than Conversion)
14
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