TLC1542_13 Datasheet, PDF (13/33 Pages) Texas Instruments – 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS

TLC1542I, TLC1542M, TLC1542Q
TLC1542C, TLC1543C, TLC1543I, TLC1543Q
www.ti.com
SLAS052G – MARCH 1992 – REVISED JANUARY 2006
PARAMETER MEASUREMENT INFORMATION (continued)
TIMING DIAGRAMS
CS
(see Note A)
I/O
CLOCK
1 2 3 4 5 6 7 8 9 10 ^{ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ} 1
Access Cycle B
Sample Cycle B
DATA
OUT
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _ADDRESS
A9
A8 A7
A6 A5 A4 A3
MSB
Previous Conversion Data
B3 B2 B1 B0
A2
A1
A0
LSB
MSB
LSB
Hi-Z State
ÎÎÎÎÎÎÎÎ^BC93 ÎÎÎÎ
EOC
Initialize
Shift in New Multiplexer Address;
Simultaneously Shift Out Previous
Conversion Value
A/D Conversion
Interval
Initialize
A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the
internal system clock after CS↓ before responding to control input signals. Therefore, no attempt should be made to
clock in an address until the minimum CS setup time has elapsed.
Figure 9. Timing for 10-Clock Transfer Using CS
CS
(see Note A)
Must be High on Power Up
I/O
CLOCK
1
2
3
4
5
6
7
8
9
10
Access Cycle B
Sample Cycle B
DATA
OUT
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _ADDRESS
A9
A8 A7 A6 A5 A4 A3
MSB
Previous Conversion Data
B3 B2 B1 B0
A2
A1
A0
LSB
MSB
LSB
1
LowLevel _{ÎÎÎÎÎÎÎÎÎÎÎÎ}BC93_{ÎÎÎÎÎÎÎÎ}
EOC
Initialize
Shift in New Multiplexer Address;
Simultaneously Shift Out Previous
Conversion Value
A/D Conversion
Interval _Initialize
A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the
internal system clock after CS↓ before responding to control input signals. Therefore, no attempt should be made to
clock in an address until the minimum CS setup time has elapsed.
Figure 10. Timing for 10-Clock Transfer Not Using CS
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