TLC1542_13 Datasheet, PDF (15/33 Pages) Texas Instruments – 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS

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TLC1542I, TLC1542M, TLC1542Q
TLC1542C, TLC1543C, TLC1543I, TLC1543Q
SLAS052G – MARCH 1992 – REVISED JANUARY 2006
PARAMETER MEASUREMENT INFORMATION (continued)
CS
(see Note A)
Must Be High on Power Up
I/O
CLOCK
1
2
3
4
5
6
7
8
Access Cycle B
Sample Cycle B
DATA
OUT
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _ADDRESS
A9
A8
MSB
A7 A6 A5 A4 A3
Previous Conversion Data
A2
B3 B2 B1 B0
MSB
LSB
9
10
A1 A0
LSB
14 15
16
1
See Note B
LowLevel ÎÎÎÎÎÎÎÎÎÎÎÎB9ÎÎÎÎÎÎÎÎ
C3
EOC
Initialize
Shift in New Multiplexer Address;
Simultaneously Shift Out Previous
Conversion Value
A/D Conversion
Interval
Initialize
A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the
internal system clock after CS↓ before responding to control input signals. Therefore, no attempt should be made to
clock in an address until the minimum CS setup time has elapsed.
B. The first I/O CLOCK must occur after the rising edge of EOC.
Figure 12. Timing for 16-Clock Transfer Not Using
CS (Serial Transfer Interval Shorter Than Conversion)
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