DS99R421_15 Datasheet, PDF (8/26 Pages) Texas Instruments – 5-43 MHz FPD-Link LVDS (3 Data + 1 Clock) to FPD-Link II LVDS (Embedded Clock DC Balanced) Converter

DS99R421
SNLS264D – JUNE 2007 – REVISED APRIL 2013
Ideal Bit Start
Sampling
Window
Ideal Bit Stop
RITOL
(Left)
RITOL
(Right)
Ideal Strobe Position
(1/2 UI)
(1 UI)
Figure 8. Receiver RITOL Left and Right
Ideal Data Bit
Beginning
DS99R421 Output
Eye Opening
Ideal Data Bit
End
Ideal Center Position (t_BIT)/2
t_BIT (1 UI)
Figure 9. Serializer Output Eye Opening
DOUT+
R_T
V_DD = (DOUT+) - (DOUT-)
DOUT-
Figure 10. Serializer V_OD Diagram
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