DS99R421_15 Datasheet, PDF (16/26 Pages) Texas Instruments – 5-43 MHz FPD-Link LVDS (3 Data + 1 Clock) to FPD-Link II LVDS (Embedded Clock DC Balanced) Converter

DS99R421
SNLS264D – JUNE 2007 – REVISED APRIL 2013
www.ti.com
Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate
switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not
required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power
pin pairs. In some cases, an external filter many be used to provide clean power to sensitive circuits such as
PLLs.
Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the LVDS
lines to prevent coupling from the LVCMOS lines to the LVDS lines. Closely-coupled differential lines of 100
Ohms are typically recommended for LVDS interconnect. The closely coupled lines help to ensure that coupled
noise will appear as common-mode and thus is rejected by the receivers. The tightly coupled lines will also
radiate less.
Termination of the LVDS interconnect is required. For point-to-point applications, termination should be located at
both ends of the devices. Nominal value is 100 Ohms to match the line’s differential impedance. Place the
resistor as close to the transmitter DOUT± outputs and receiver RIN± inputs as possible to minimize the resulting
stub between the termination resistor and device.
LVDS INTERCONNECT GUIDELINES
See AN-1108 (SNLA008) and AN-905 (SNLA035) for full details.
• Use 100Ω coupled differential pairs
• Use the S/2S/3S rule in separation
– S = space between the pair
– 2S = space between pairs
– 3S = space to LVCMOS signal
• Minimize the number of vias
• Use differential connectors when operating above 500Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
• Terminate as close to the TX outputs and RX inputs as possible
Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the TI
web site at: http://www.ti.com/ww/en/analog/interface/lvds.shtml
Functional Overview
RxCLKIN
(Differential)
V_diff = 0V
Previous Cycle
RxIN0
R1-1
R0-1
RxIN1
G2-1
G1-1
RxIN2
B3-1
B2-1
G0
(bit 6)
B1
(bit13)
DE
(bit20)
V_diff = 0V
Current Cycle
R5
(bit5)
R4
(bit4)
R3
(bit3)
R2
(bit2)
B0
(bit12)
G5
(bit11)
G4
(bit10)
G3
(bit9)
VSYNC
(bit19)
HSYNC
(bit18)
B5
(bit17)
B4
(bit16)
V_diff = 0V
Next
Cycle
R1
(bit1)
R0
(bit0)
G2
(bit8)
G1
(bit7)
B3
(bit15)
B2
(bit14)
Figure 12. FPD-Link LVDS Input Mapping (3 LVDS Data + 1 LVDS Clock)
16
Submit Documentation Feedback
Product Folder Links: DS99R421
Copyright © 2007–2013, Texas Instruments Incorporated