DS99R421_15 Datasheet, PDF (15/26 Pages) Texas Instruments – 5-43 MHz FPD-Link LVDS (3 Data + 1 Clock) to FPD-Link II LVDS (Embedded Clock DC Balanced) Converter

DS99R421
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APPLICATIONS INFORMATION
SNLS264D – JUNE 2007 – REVISED APRIL 2013
USING THE DS99R421 AND DS90UR124
The DS99R421 allows a FPD-Link based bus to connect to a single-channel serial LVDS interface in a Display
using the latest generation LVDS Deserializer (DS90UR124). This allows for existing hosts with FPD-Link
interfaces to be further serialized into a single pair and connect with the current generation Display Deserializer.
Systems benefit by the smaller interconnect (reduced pins, less size, lower cost).
DISPLAY APPLICATION
18-bit color depth (RGB666) and up to 1280 X 480 display formats can be supported. In a RGB666 configuration
18 color bits (R[5:0], G [5:0], B[5:0]), Pixel Clock (PCLK) and three control bits (VS, HS and DE) along with three
low speed spare bits OS[2:0] are supported across the serial link with PCLK rates from 5 to 43MHz.
TYPICAL APPLICATION CONNECTION
Figure 15 shows a typical connection to the DS99R421.
The 4 pairs of FPD-Link LVDS interface are the input interface along with the optional over-sampled control
signals. Termination of the LVDS signals is provided internally by the DS99R421 device.
The single channel LVDS serial output requires an external termination and also AC coupling capacitors.
Configuration pins for the typical application are shown:
• DEN – tie HIGH if unused.
• PWDNB – Sleep / Enable Control Input – Connect to host or tie HIGH
• BISTEN – tie LOW if not used, or connect or host
• VODSEL – tie LOW for normal VOD magnitude (application dependant)
• PRE – Leave open if not required (have a R pad option on PCB)
• RESRVD – tie LOW (4 pins)
There are 4 power rails for the device. These may be bussed together on a common 3.3V plane. At a minimum,
four 0.1uF capacitors should be used for local bypassing.
With the above configuration a FPD-Link interface along with three additional low-speed signals are converted to
a single serial LVDS channel.
PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS
Circuit board layout and stack-up for the LVDS SERDES devices should be designed to provide low-noise power
feed to the device. Good layout practice will also separate high frequency or high-level inputs and outputs to
minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly
improved by using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane
capacitance for the PCB power system with low-inductance parasitics, which has proven especially effective at
high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass
capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the
range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range. Voltage rating of the
tantalum capacitors should be at least 5X the power supply voltage being used.
Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per
supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power
entry. This is typically in the 50uF to 100uF range and will smooth low frequency switching noise. It is
recommended to connect power and ground pins directly to the power and ground planes with bypass capacitors
connected to the plane with vias on both ends of the capacitor. Connecting power or ground pins to an external
bypass capacitor will increase the inductance of the path.
A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size
reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of
these external bypass capacitors, usually in the range of 20-30 MHz range. To provide effective bypassing,
multiple capacitors are often used to achieve low impedance between the supply rails over the frequency of
interest. At high frequency, it is also a common practice to use two vias from power and ground pins to the
planes, reducing the impedance at high frequency.
Copyright © 2007–2013, Texas Instruments Incorporated
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