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| DS99R421_15 Datasheet, PDF (7/26 Pages) Texas Instruments – 5-43 MHz FPD-Link LVDS (3 Data + 1 Clock) to FPD-Link II LVDS (Embedded Clock DC Balanced) Converter | |||
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www.ti.com
DS99R421
SNLS264D â JUNE 2007 â REVISED APRIL 2013
RxCLKIN
(Differential)
Vdiff = 0V
Previous Cycle
RxIN0
R1-1
R0-1
RxIN1
G2-1
G1-1
RxIN2
B3-1
B2-1
Vdiff = 0V
Current Cycle
Vdiff = 0V
Next
Cycle
G0
R5
R4
R3
R2
R1
R0
B1
B0
G5
G4
G3
G2
G1
DE
VSYNC HSYNC
B5
B4
B3
B2
Figure 6. Receiver LVDS Input Mapping
RxCLKIN
(Differential)
Vdiff = 0V
Previous Cycle
RxIN0
R1-1
R0-1
G0
Vdiff = 0V
Current Cycle
Vdiff = 0V
Next
Cycle
R5
R4
R3
R2
R1
R0
RxIN1
G2-1
G1-1
B1
B0
G5
G4
G3
G2
G1
RxIN2
B3-1
B2-1
DE
VSYNC
HSYNC
B5
B4
B3
B2
RITOL1 min
RITOL1 max
RITOL0 min
RITOL0 max
RITOL6 min
RITOL6 max
RITOL5 min
RITOL5 max
RITOL4 min
RITOL4 max
RITOL3 min
RITOL3 max
RITOL2 min
RITOL2 max
Figure 7. Receiver RITOL Min and Max
Copyright © 2007â2013, Texas Instruments Incorporated
Product Folder Links: DS99R421
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