DS99R421_15 Datasheet, PDF (11/26 Pages) Texas Instruments – 5-43 MHz FPD-Link LVDS (3 Data + 1 Clock) to FPD-Link II LVDS (Embedded Clock DC Balanced) Converter

DS99R421
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FUNCTIONAL DESCRIPTION
SNLS264D – JUNE 2007 – REVISED APRIL 2013
The DS99R421 is a Video Interface converter. It converts an FPD-Link interface (3 LVDS data channels + 1
LVDS Clock, e.g. DS90C365A or equivalent) plus up to three (3) LVCMOS additional signals into a single high-
speed LVDS serial Interface (see Figure 13).
The 21 bits of data from the FPD-Link Interface are serialized along with the 3 additional over-sampled bits
(OS[2:0]) into a randomized, scrambled and DC Balanced data stream to support AC coupling and to enhance
the signal eye opening. Four (4) additional overhead bits are sent per clock which provides the embedded clock
and serial link control information. The embedded clock LVDS serial stream has an effective data throughput of
120 Mbps (5MHz X 24) to 1.03 Gbps (43MHz X 24). The DS99R421 Line Driver is designed to transmit data up
to 10 meters over shielded twisted pair (STP) at signaling rates up to 1.2Gbps (43MHz X 28).
The DS90UR124 receiver converts the embedded clock LVDS stream back into a 24-bit wide LVCMOS parallel
bus and the recovered low-speed clock.
Note: The DS90C124 is not compatible with the DS99R421.
LINK START UP
The start up of the DS99R421 involves only one PLL Lock time. The FPD-Link Receiver side must lock to its
incoming LVDS RxCLKIN. The Serializer side then extracts its reference clock from the incoming LVDS clock. At
the far end of the link, the Deserializer (DS90UR124) also needs to detect the LVDS signals and lock to the
incoming serial stream, drives the LOCK pin HIGH, before outputting valid data. Note that when using a Bus
Converter (FPD-Link to Serial) additional time is required in the start up to account for the additional PLLs in the
path.
TYPICAL START UP SEQUENCE
1. FPD-Link Stream is applied to the DS99R421 inputs.
2. With power applied and the DS99R421 enabled, it will lock to the incoming FPD-Link clock. Until the
DS99R421 is ready, it will hold its outputs in TRI-STATE. Once the locking is complete, valid serial payloads
are sent across the link to the DES (DS90UR124).
3. With power applied and the device enabled, the DS90UR124 will lock to the incoming serial stream. Until the
DS90UR124 is locked, outputs are in TRI-STATE and its LOCK output pin is held Low. After Lock, the
DS90UR124 outputs are active and LOCK is HIGH.
DATA TRANSFER
After the link start up, the DS99R421 provides a streaming video interface. For each Pixel Clock (PCLK) received
from the FPD-Link Interface 21 bits of information are recovered along with the PCLK. The 21 bits of information
include the 18-bits of RGB information and the three video control signals (HS, VS and DE). The over-sample
control bits are also sampled in this PCLK domain and appended to the 21 bits of information for a 24-bit total
payload. The Serializer side now takes this data and performs four operations to it. First the data is randomized,
second the data is scrambled, third the data is balanced, and finally the serial link control and clock embedding is
done. The Serializer transmits 28 bits of information per payload to the Deserializer per PCLK. See DS90UR241
datasheet for additional information on the Serializer’s description and operation.
The chipset supports PCLK frequency ranges of 5 MHz to 43 MHz. At the 43MHz PCLK rate, 28 bits are sent
across the serial link at 1.2Gbps. The link is very efficient, sending 25 bits of information (18 RGB, 3 control, 3
over-sample control, and PCLK) with 28 serial bits. This yields 89% efficiency.
DS99R421 LINE DRIVER
The DS99R421 output (DOUT±) is used to drive a point-to-point connection as shown in Figure 14. The Line
driver transmits data when the data enable pin (DEN) is HIGH, the power down bar (PWDNB) is HIGH, and the
device is locked to the incoming FPD-Link stream. If the DEN is set LOW, the device remains locked, but the
driver outputs are placed in TRI-STATE. This maybe used to provide a fast start up since a lock time is not
required.
Copyright © 2007–2013, Texas Instruments Incorporated
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