DS99R421_15 Datasheet, PDF(14/26 Page) Texas Instruments – 5-43 MHz FPD-Link LVDS (3 Data + 1 Clock) to FPD-Link II LVDS (Embedded Clock DC Balanced) Converter

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DS99R421_15 Datasheet, PDF (14/26 Pages) Texas Instruments – 5-43 MHz FPD-Link LVDS (3 Data + 1 Clock) to FPD-Link II LVDS (Embedded Clock DC Balanced) Converter

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DS99R421

SNLS264D â JUNE 2007 â REVISED APRIL 2013

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and OS[2:0] are ignored during operation of the BIST. The BISTM pin on the DS90UR124 selects the error

reporting status mode of the BIST function. When BIST is configured in the error status mode (BISTM = LOW),

each of the ROUT[23:0] outputs of the DS90UR124 will correspond to bit errors on a cycle-by-cycle basis. The

result of bit mismatches are indicated on the respective parallel inputs on the ROUT[23:0] data output pins. In the

BIST error count accumulator mode (BISTM = HIGH), an 8-bit counter on ROUT[7:0] is used to represent the

number of errors detected (0 to 255 max). The successful completion of the BIST test is reported on the PASS

pin on the DS90UR124 Deserializer. The DS90UR124 Deserializer's PLL must first be locked to ensure the

PASS status is valid. The PASS status pin will stay LOW and then transition to HIGH once a BER of 1x10-9 is

achieved across the transmission link.

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