DS99R124AQ_14 Datasheet, PDF (8/31 Pages) Texas Instruments – 5 - 43 MHz 18-bit Color FPD-Link II to FPD-Link Converter

DS99R124AQ
SNLS342A – JULY 2011 – REVISED APRIL 2013
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Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.⁽¹⁾⁽²⁾
Parameter
Test Conditions
Pin/Freq.
Min
FPD-Link II
t_DDLT
Lock Time⁽³⁾
SSCG = Off
SSCG = On
SSCG = Off
5 MHz
5 MHz
43 MHz
SSCG = On
43 MHz
t_DJIT
Input Jitter Tolerance
EQ = Off
Jitter Frequency > 10 MHz
FPD-Link Output
t_TLHT
t_THLT
t_DCCJ
Low to High Transition Time
High to Low Transition Time
R_L = 100Ω
Cycle-to-Cycle Output Jitter^{(4)(5) TxCLKOUT = 5 MHz}
TxCLKOUT = 43 MHz
TxCLKOUT±,
TxOUT[2:0]±
TxCLKOUT±
t_TTP1
Transmitter Pulse Position for
bit 1
t_TTP0
Transmitter Pulse Position for
bit 0
t_TPP6
Transmitter Pulse Position for
bit 6
t_TTP5
Transmitter Pulse Position for
bit 5
TxOUT[2:0]±
t_TTP4
Transmitter Pulse Position for
bit 4
t_TTP3
Transmitter Pulse Position for
bit 3
t_TTP2
Transmitter Pulse Position for
bit 2
t_TPDD
Power Down Delay active to
OFF, Figure 6
TxCLKOUT = 43 MHz
t_TXZR
Enable Delay OFF to active
Figure 7
TxCLKOUT = 43 MHz
LVCMOS Outputs
t_CLH
t_CHL
t_PASS
Low to High Transition Time
High to Low Transition Time
BIST PASS Valid Time,
BISTEN = 1, Figure 12
C_L = 8 pF, Figure 5
TxCLKOUT = 5 MHz
TxCLKOUT = 43 MHz
LOCK, PASS, OS[2:0]
PASS
SSCG Mode
f_DEV
Spread Spectrum Clocking
Deviation Frequency
See ⁽⁶⁾
TxCLKOUT = 5 to 43
MHz, SSC[3:0] = ON
±0.5
f_MOD
Spread Spectrum Clocking
Modulation Frequency
See ⁽⁶⁾
TxCLKOUT = 5 to 43
MHz, SSC[3:0] = ON
8
Typ Max Units
6
ms
14
ms
5
ms
8
ms
>0.45
UI
0.3
0.6
ns
0.3
0.6
ns
900 2100 ps
75
125
ps
0
UI
1
UI
2
UI
3
UI
4
UI
5
UI
6
UI
6
10
ns
40
55
ns
10
15
ns
10
15
ns
560
570
ns
70
75
ns
±2
%
100 kHz
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(2) Typical values represent most likely parametric norms at V_DDn = 1.8V, V_DDTX = 3.3V, V_DDIO = 1.8V or 3.3V, Ta = +25 °C, and at the
Recommended Operation Conditions at the time of product characterization and are not ensured.
(3) t_DDLT is the time required by the deserializer to obtain lock when exiting power-down state with an active PCLK.
(4) t_DCCJ is the maximum amount of jitter between adjacent clock cycles.
(5) Specification is ensured by characterization and is not tested in production.
(6) Specification is ensured by design and is not tested in production.
8
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