DS99R124AQ_14 Datasheet, PDF (14/31 Pages) Texas Instruments – 5 - 43 MHz 18-bit Color FPD-Link II to FPD-Link Converter

DS99R124AQ
SNLS342A – JULY 2011 – REVISED APRIL 2013
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FUNCTIONAL DESCRIPTION
The DS99R124AQ receives 24-bits of data over a single serial FPD-Link II pair operating at 140Mbps to
1.2Gbps. The serial stream also contains an embedded clock, and the DC-balance information which enhances
signal quality and supports AC coupling. The receiver copnverts the serial stream into a 4-channel (3 data and 1
clock) FPD-Link LVDS Interface. The device is intended to be used with the DS90UR241or the DS99R421 FPD-
Link II serializers.
The Des converts a single input serial data stream to a FPD-Link output bus, and also provides a signal check
for the chipset Built In Self Test (BIST) mode. The device can be configured via external pins or through the
optional serial control bus. The Des features enhance signal quality on the link by supporting the FPD-Link II
data coding that provides randomization, scrambling, and DC balancing of the data. The Des includes multiple
features to reduce EMI associated with display data transmission. This includes the randomization and
scrambling of the data, FPD-Link LVDS Output interface, and also the output spread spectrum clock generation
(SSCG) support. The Des' power saving features include a power down mode, and optional LVCMOS (1.8 V)
interface compatibility.
The Des can attain lock to a data stream without the use of a separate reference clock source, which greatly
simplifies system complexity and overall cost. The Des also synchronizes to the Ser regardless of the data
pattern, delivering true automatic “plug and lock” performance. It can lock to the incoming serial stream without
the need of special training patterns or sync characters. The Des recovers the clock and data by extracting the
embedded clock information, validating and then deserializing the incoming data stream.
The DS99R421Q / DS99R124AQ chipset supports 18-bit color depth, HS, VS and DE video control signals and
up to three over-sampled low-speed (general purpose) data bits.
DATA TRANSFER
The DS99R124AQ will receive a pixel of data in the following format: C1 and C0 represent the embedded clock
in the serial stream. C1 is always HIGH and C0 is always LOW. b[23:0] contain the scrambled data. DCB is the
DC-Balanced control bit. DCB is used to minimize the short and long-term DC bias on the signal lines. This bit
determines if the data is unmodified or inverted. DCA is used to validate data integrity in the embedded data
stream. Both DCA and DCB coding schemes are generated by the Ser and decoded by the Des automatically.
Figure 17 illustrates the serial stream per PCLK cycle.
C
1
b
0
b
1
b
2
b
3
b
4
b
5
b
6
b
7
b
8
b
9
b
1
0
b
1
1
D
C
A
D
C
B
b
1
2
b
1
3
b
1
4
b
1
5
b
1
6
b
1
7
b
1
8
b
1
9
b
2
0
b
2
1
b
2
2
b
2
3
C
0
Figure 17. FPD-Link II Serial Stream (DS99R421/DS99R124A)
The device supports clocks in the range of 5 MHz to 43 MHz. With every clock cycle 24 bits of payload are
received along with the four overhead bits. Thus, the line rate is 1.2 Gbps maximum (140 Mbps minimum) with
an effective data rate of 1.03 Gbps maximum. The link is extremely efficient at 86% (24/28).
The FPD-Link output will pass along the data to the Display in the format shown in Figure 18.
TxCLKOUT
TxOUT0 G0 R5 R4 R3 R2 R1 R0
TxOUT1 B1 B0 G5 G4 G3 G2 G1
TxOUT2 DE VS HS B5 B4 B3 B2
Figure 18. FPD-Link Output Format
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