DS99R124AQ_14 Datasheet, PDF (16/31 Pages) Texas Instruments – 5 - 43 MHz 18-bit Color FPD-Link II to FPD-Link Converter

DS99R124AQ
SNLS342A – JULY 2011 – REVISED APRIL 2013
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PDB
H
H
INPUTS
OEN
L
H
Table 1. Output State Table (continued)
OSS_SEL
X
X
LOCK
H
H
OUTPUTS
OTHER OUTPUTS
TxCLKOUT is TRI-STATE
TxOUT[2:0] areTRI-STATE
OS[2:0] are Active
PASS is Active
(This setting allows the system to run BIST or use the OS[2:0]
bits while the panel is off)
TxCLKOUT is Active
TxOUT[2:0] are Active
OS[2:0] are Active
PASS is Active
(Normal operating mode)
LVCMOS 1.8V / 3.3V VDDIO Operation
The LVCMOS inputs and outputs can operate with 1.8 V or 3.3 V levels (V_DDIO) for target (Display) compatibility.
The 1.8 V levels will offer a lower noise (EMI) and also a system power savings.
FPD-LINK OUTPUT
VODSEL
The differential output voltage of the FPD-Link interface is controlled by the VODSEL input.
VODSEL
L
H
Table 2. VODSEL Configuration Table
Result
VOD is 250mV TYP (500mVp-p)
VOD is 400mV TYP (800mVp-p)
SSCG Generation — Optional
The Des provides an internally generated spread spectrum clock (SSCG) to modulate its outputs. Both clock and
data outputs are modulated. This will aid to lower system EMI. Output SSCG deviations to ±2.0% (4% total) at up
to 35kHz modulations nominally are available. See Table 3 and Table 4. This feature may be controlled by pins
or by register. The LFMODE should be set appropriately if the SSCG is being used. Set LFMODE High if the
clock frequency is between 5 MHz and 20 MHz, set LFMODE Low if the clock frequency is between 20 MHz and
43 MHz.
SSC2
L
L
L
L
H
H
H
H
Table 3. SSCG Configuration (LFMODE = L) — Des Output
SSC[2:0] Inputs
LFMODE = L (20 - 43 MHz)
SSC1
L
L
H
H
L
L
H
H
SSC0
L
H
L
H
L
H
L
H
fdev (%)
OFF
±0.9
±1.2
±1.9
±2.3
±0.7
±1.3
±1.7
Result
fmod (kHz)
OFF
CLK/2168
CLK/1300
16
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