DS99R124AQ_14 Datasheet, PDF (18/31 Pages) Texas Instruments – 5 - 43 MHz 18-bit Color FPD-Link II to FPD-Link Converter

DS99R124AQ
SNLS342A – JULY 2011 – REVISED APRIL 2013
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Normal
Step 1: SER in BIST
BIST
Wait
Step 2: Wait, DES in BIST
BIST
Start
Step 3: DES in Normal
Mode - check PASS
BIST
Stop
Step 4: SER in Normal
Figure 20. BIST Mode Flow Diagram
Sample BIST Sequence
See Figure 20 for the BIST mode flow diagram.
Step 1: For the DS99R421 FPD-Link II Ser BIST Mode is enabled via the BISTEN pin. For the DS90UR241 Ser,
BIST mode is enetered by setting all the input data of the device to Low state. A PCLK is required for all the Ser
options. When the Des detects the BIST mode pattern and command (DCA and DCB code) the RGB and control
signal outputs are shut off.
Step 2: Place the DS99R124AQ Des in BIST mode by setting the BISTEN = H. The Des is now in the BIST
mode. If BISTM = H, the Des will check the incoming serial payloads for errors. If an error in the payload (1 to
24) is detected, the PASS pin will switch low for one half of the clock period. During the BIST test, the PASS
output can be monitored and counted to determine the payload error rate.
Step 3: To Stop the BIST mode, the Des BISTEN pin is set Low. The Des stops checking the data. The final test
result is held on the PASS pin. If the test ran error free, the PASS output will be High. If there was one or more
errors detected, the PASS output will be Low. The PASS output state is held until a new BIST is run, the device
is RESET, or Powered Down. The BIST duration is user controlled by the duration of the BISTEN signal.
Step 4: To return the link to normal operation, the Ser BISTEN input is set Low. The Link returns to normal
operation.
Figure 21 shows the waveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2
shows one with multiple errors. In most cases it is difficult to generate errors due to the robustness of the link
(differential data transmission etc.), thus they may be introduced by greatly extending the cable length, faulting
the interconnect, reducing signal condition enhancements (De-Emphasis, VODSEL, or Rx Equalization).
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