DS90CR483_15 Datasheet, PDF (8/27 Pages) Texas Instruments – 48-Bit LVDS Channel Link SER/DES - 33 - 112 MHz

DS90CR483, DS90CR484
SNLS047H – FEBRUARY 2000 – REVISED APRIL 2013
AC Timing Diagrams
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The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
Figure 1. “Worst Case” Test Pattern
Figure 2. DS90CR483 (Transmitter) LVDS Output Load and Transition Times
Figure 3. DS90CR484 (Receiver) CMOS/TTL Output Load and Transition Times
Figure 4. DS90CR483 (Transmitter) Input Clock Transition Time
Figure 5. DS90CR483 (Transmitter) Setup/Hold and High/Low Times
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