DS90CR483_15 Datasheet, PDF (17/27 Pages) Texas Instruments – 48-Bit LVDS Channel Link SER/DES - 33 - 112 MHz

DS90CR483, DS90CR484
www.ti.com
For more information:
Channel Link Applications Notes currently available:
• AN-1041 Introduction to Channel Link
• AN-1059 RSKM Calculations
• AN-1108 PCB and Interconnect Guidelines
• AN-905 Differential Impedance
• LVDS Owner’s Manual
SNLS047H – FEBRUARY 2000 – REVISED APRIL 2013
Typical Data Rate vs Cable Length Curve
1000
V_CC = 3.3V, Pre = 100%
100
V_CC = 3.3V, Pre = 0%
10
1 2 3 4 5 6 7 10 1112 1314 15 1617 18
CABLE LENGTH (m)
DATA RATE VS CABLE LENGTH TEST PROCEDURE
The Data Rate vs Cable Length graph was generated using CLINK3V48BT-112 Evaluation Kit and 3M’s Mini D
Ribbon (MDR) Cable under typical conditions (Vcc = 3.3V, Temp = +25°C). A Tektronix MB100 Bit-Error-Rate
Tester (BERT) was used to send a PRBS (2¹⁵) pattern to 32 of the 48 input channels on the transmitter
(DS90CR483). The BERT was also used to monitor the corresponding 32 receiver (DS90CR484) output
channels for bit errors. The frequency of the input signal were increased until bit errors were reported on the
BERT. The frequency on the graph is the highest frequency without error.
Results:
The DS90CR483/4 link was error free at 100MHz over 10 meters of 3M cable using pre-emphasis and DC
balance mode off.
Pin Name
TxIN
TxOUTP
TxOUTM
TxCLKIN
TxCLKP
TxCLKM
PD
PLLSEL
DS90CR483 PIN DESCRIPTION—Channel Link Transmitter
I/O
I
TTL level input⁽¹⁾
Description
O
Positive LVDS differential data output.
O
Negative LVDS differential data output.
I
TTL level clock input. The rising edge acts as data strobe.
O
Positive LVDS differential clock output.
O
Negative LVDS differential clock output.
I
TTL level input. Assertion (low input) tri-states the outputs, ensuring low current at power down⁽¹⁾
I
PLL range select. This pin should be tied to V_CC for auto-range. Tied to ground or NC will force the
PLL to low range only. Typical shift point is between 55 and 68 MHz for auto-range.⁽¹⁾⁽²⁾
(1) Inputs default to “low” when left open due to internal pull-down resistor.
(2) The PLL range shift point is in the 55 - 68 MHz range, typically the shift will occur during the lock time. For 65-70 MHz applications, the
DS90CR481/2 is recommended since its shift point is below its operation range. See Applications Information section.
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Product Folder Links: DS90CR483 DS90CR484