DS90CR483_15 Datasheet, PDF (16/27 Pages) Texas Instruments – 48-Bit LVDS Channel Link SER/DES - 33 - 112 MHz

DS90CR483, DS90CR484
SNLS047H – FEBRUARY 2000 – REVISED APRIL 2013
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Supply Bypass Recommendations:
Bypass capacitors must be used on the power supply pins. Different pins supply different portions of the circuit,
therefore capacitors should be nearby all power supply pins except as noted in the and tables. Use high
frequency ceramic (surface mount recommended) 0.1µF capacitors close to each supply pin. If space allows, a
0.01µF capacitor should be used in parallel, with the smallest value closest to the device pin. Additional scattered
capacitors over the printed circuit board will improve decoupling. Multiple (large) via should be used to connect
the decoupling capacitors to the power plane. A 4.7 to 10 µF bulk cap is recommended near the PLLVCC pins
and also the LVDSVCC (pin #40) on the Transmitter. Connections between the caps and the pin should use wide
traces.
Input Signal Quality Requirements - Transmitter:
The input signal quality must comply to the datasheet requirements, please refer to the Recommended
Transmitter Input Characteristics table for specifications. In addition undershoots in excess of the ABS MAX
specifications are not recommended. If the line between the host device and the transmitter is long and acts as a
transmission line, then termination should be employed. If the transmitter is being driven from a device with
programmable drive strengths, data inputs are recommended to be set to a weak setting to prevent transmission
line effects. The clock signal is typically set higher to provide a clean edge that is also low jitter.
Unused LVDS Outputs:
Unused LVDS output channels should be terminated with 100 Ohm at the transmitter’s output pin.
Receiver output drive strength:
The DS90CR484 output specify a 8pF load, V_OH and V_OL are tested at ± 2mA, which is intended for only 1 or
maybe 2 loads. If high fan-out is required or long transmission line driving capability, buffering the receiver output
is recommended. Receiver outputs do not support / provide a TRI-STATE function.
LVDS Interconnect Guidelines:
See AN-1108 and AN-905 for full details.
• Use 100Ω coupled differential pairs
• Use the S/2S/3S rule in spacings
– S = space between the pair
– 2S = space between pairs
– 3S = space to TTL signal
• Minimize the number of VIA
• Use differential connectors when operating above 500Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
• Minimize skew between pairs
• Terminate as close to the RXinputs as possible
DS90CR481/482 and PLLSEL Function
The DS90CR481/2 chipset is electrically similar to the DS90CR483/4. The DS90CR481/2 differ only in the
control circuit of the internal PLL and are specified for 65 to 112 MHz operation. The devices will directly inter-
operate within the scope of the respective datasheets. The DS90CR483/4 supports a wide operating range from
33 to 112 MHz. The PLLSEL pin is used to select an auto-range feature. It shifts between the two ranges (High
and Low) in the 55 to 68 MHz range. For operation in the 65 to 70 MHz range, the DS90CR481/2 is
recommended as it will select High gear only and offer more margin to the system.
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