DS90CR483_15 Datasheet, PDF (18/27 Pages) Texas Instruments – 48-Bit LVDS Channel Link SER/DES - 33 - 112 MHz

DS90CR483, DS90CR484
SNLS047H – FEBRUARY 2000 – REVISED APRIL 2013
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DS90CR483 PIN DESCRIPTION—Channel Link Transmitter (continued)
Pin Name
PRE
DS_OPT
BAL
V_CC
GND
PLLV_CC
PLLGND
LVDSV_CC
LVDSGND
NC
I/O
Description
Pre-emphasis “level” select. Pre-emphasis is active when input is tied to V_CC through external pull-
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up resistor. Resistor value determines Pre-emphasis level (See APPLICATIONS INFORMATION
Section). For normal LVDS drive level (No Pre-emphasis) leave this pin open (do not tie to
ground).
Cable Deskew performed when TTL level input is low. No TxIN data is sampled during Deskew.
To perform Deskew function, input must be held low for a minimum of 4 clock cycles. The Deskew
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operation is normally conducted after the TX and RX PLLs have locked. It should also be
conducted after a system reset, or a reconfiguration event. It must be performed at least once
when "DESKEW" is enabled.⁽¹⁾ Deskew is only supported in the DC Balance mode (BAL = High).
TTL level input. This pin was previously labeled as V_CC, which enabled the DC Balance function.
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But when tied low or left open, the DC Balance function is disabled. Please refer to Figure 15 and
Figure 16 for LVDS data bit mapping respectively.⁽¹⁾⁽³⁾
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Power supply pins for TTL inputs and digital circuitry. Bypass not required on Pins 20 and 21.
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Ground pins for TTL inputs and digital circuitry.
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Power supply pin for PLL circuitry.
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Ground pins for PLL circuitry.
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Power supply pin for LVDS outputs.
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Ground pins for LVDS outputs.
No Connect. Make NO Connection to these pins - leave open.
(3) The DS90CR484 is design to automatically detect the DC Balance or non-DC Balance transmitted data from the DS90CR483 and
deserialize the LVDS data according to the define bit mapping.
RxINP
RxINM
RxOUT
Pin Name
RxCLKP
RxCLKM
RxCLKOUT
PLLSEL
DESKEW
PD
V_CC
GND
PLLV_CC
PLLGND
LVDSV_CC
LVDSGND
NC
DS90CR484 PIN DESCRIPTION—Channel Link Receiver
I/O
Description
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Positive LVDS differential data inputs.
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Negative LVDS differential data inputs.
O
TTL level data outputs. In PowerDown (PD = Low) mode, receiver outputs are
forced to a Low state.
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Positive LVDS differential clock input.
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Negative LVDS differential clock input.
O
TTL level clock output. The rising edge acts as data strobe.
PLL range select. This pin should be tied to V_CC for auto-range. Tied to ground or
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NC will force the PLL to low range only. Typical shift point is between 55 and 68
MHz for auto-range. ^{(1) (2)}
Deskew / Oversampling “on/off” select. When using the Deskew / Oversample
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feature this pin must be tied to V_CC. Tieing this pin to ground disables this
feature. Deskew is only supported in the DC Balance mode.⁽¹⁾
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TTL level input. When asserted (low input) the receiver outputs are Low.⁽¹⁾
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Power supply pins for TTL outputs and digital circuitry. Bypass not required on
Pins 6 and 77.
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Ground pins for TTL outputs and digital circuitry.
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Power supply for PLL circuitry.
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Ground pin for PLL circuitry.
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Power supply pin for LVDS inputs.
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Ground pins for LVDS inputs.
No Connect. Make NO Connection to these pins - leave open.
(1) Inputs default to “low” when left open due to internal pull-down resistor.
(2) The PLL range shift point is in the 55 - 68 MHz range, typically the shift will occur during the lock time. For 65-70 MHz applications, the
DS90CR481/2 is recommended since its shift point is below its operation range. See Applications Information section.
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