DS90CR483_15 Datasheet, PDF (14/27 Pages) Texas Instruments – 48-Bit LVDS Channel Link SER/DES - 33 - 112 MHz

DS90CR483, DS90CR484
SNLS047H – FEBRUARY 2000 – REVISED APRIL 2013
www.ti.com
The value of the DC balance bit (DCBAL) shall be 0 when the data is sent unmodified and 1 when the data is
sent inverted. To determine whether to send data unmodified or inverted, the running word disparity and the
current data disparity are used. If the running word disparity is positive and the current data disparity is positive,
the data shall be sent inverted. If the running word disparity is positive and the current data disparity is zero or
negative, the data shall be sent unmodified. If the running word disparity is negative and the current data
disparity is positive, the data shall be sent unmodified. If the running word disparity is negative and the current
data disparity is zero or negative, the data shall be sent inverted. If the running word disparity is zero, the data
shall be sent inverted.
DC Balance mode is set when the BAL pin on the transmitter is tied HIGH - see . DC Balancing is useful on long
cable applications which are typically greater than 5 meters in length.
3. Deskew:
Deskew is supported in the DC Balance mode only (BAL = high on DS90CR483). The “DESKEW” pin on the
receiver when set high will deskew a minimum of ±1 LVDS data bit time skew from the ideal strobe location
between signals arriving on independent differential pairs (pair-to-pair skew). It is required that the “DS_OPT” pin
on the Transmitter must be applied low for a minimum of four clock cycles to complete the deskew operation. It is
also required that this must be performed at least once at any time after the PLLs have locked to the input clock
frequency. If power is lost, or if the cable has been switched, this procedure must be repeated or else the
receiver may not sample the incoming LVDS data correctly. When the receiver is in the deskew mode, all
receiver data outputs are set to a LOW state, but the receiver clock output is still active and switching. Setting
the “DESKEW” pin to low will disable the deskew operation and allow the receiver to operation on a fixed data
sampling strobe. In this case, the ”DS_OPT” pin on the transmitter must then be set high.
The DS_OPT pin at the input of the transmitter (DS90CR483) is used to initiate the deskew calibration pattern. It
must be applied low for a minimum of four clock cycles in order for the receiver to complete the deskew
operation. For this reason, the LVDS clock signal with DS_OPT applied high (active data sampling) shall be
1111000 or 1110000 pattern. During the deskew operation with DS_OPT applied low, the LVDS clock signal
shall be 1111100 or 1100000 pattern. The transmitter will also output a series of 1111000 or 1110000 onto the
LVDS data lines (TxOUT 0-7) during deskew so that the receiver can automatically calibrated the data sampling
strobes at the receiver inputs. Each data channel is deskewed independently and is tuned with a step size of 1/3
of a bit time over a range of +/−1 TBIT from the ideal strobe location. The Deskew feature operates up to clock
rates of 80 MHz only. If the Receiver is enabled in the deskew mode, then it must be trained before data transfer.
Clock Jitter:
The transmitter is designed to reject cycle-to-cycle jitter which may be seen at the transmitter input clock. Very
low cycle-to-cycle jitter is passed on to the transmitter outputs. Cycle-to-cycle jitter has been measured over
frequency to be less than 100 ps with input step function jitter applied. This should be subtracted from the
RSKM/RSKMD budget as shown and described in Figure 13 and Figure 14. This rejection capability significantly
reduces the impact of jitter at the TXinput clock pin, and improves the accuracy of data sampling in the receiver.
Transmitter output jitter is effected by PLLVCC noise and input clock jitter - minimize supply noise and use a low
jitter clock source to limit output jitter. The falling edge of the input clock to the transmitter is the critical edge and
is used by the PLL circuit.
RSKM - Receiver Skew Margin
RSKM is a chipset parameter and is explained in AN-1059 in detail. It is the difference between the transmitter’s
pulse position and the receiver’s strobe window. RSKM must be greater than the summation of: Interconnect
skew, LVDS Source Clock Jitter (TJCC), and ISI (if any). See Figure 13. Interconnect skew includes PCB traces
differences, connector skew and cable skew for a cable application. PCB trace and connector skew can be
compensated for in the design of the system. Cable skew is media type and length dependant.
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