DS90C3202_13 Datasheet, PDF (8/26 Pages) Texas Instruments – 3.3V 8 MHz to 135 MHz Dual FPD-Link Receiver

DS90C3202
SNLS191D – APRIL 2005 – REVISED APRIL 2013
AC Timing Diagrams
SCD:TF
SCD:TR
S2CLK
f_SC
SC:LOW
SC:HIGH
SU:STA
S2DAT
Data in
HD:STA
SD:SC
SC:SD
HD:STO
S2DAT
Data out
SCL:SD
Figure 3. Two-Wire Serial Communication Interface Timing Diagram
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Figure 4. “Worst Case” Test Pattern
TCLKIN
TXOA, TXEA
TXOB, TXEB
TXOC, TXEC
TXOD, TXED
TXOE, TXEE
Figure 5. Incremental Test Pattern
600
Worst Case
(max)
500
400
Worst Case
(typ)
300
200
100
0
0
Incr. Pattern Incr. Pattern
(max)
(typ)
20 40 60 80 100 120 140 160
FREQUENCY (MHz)
Figure 6. Typical and Max ICC with Worse Case and Incremental Pattern
8
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