DS90C3202_13 Datasheet, PDF (20/26 Pages) Texas Instruments – 3.3V 8 MHz to 135 MHz Dual FPD-Link Receiver

DS90C3202
SNLS191D – APRIL 2005 – REVISED APRIL 2013
www.ti.com
The master must generate a “Start” by sending the 7-bit slave address plus a 0 and wait for acknowledge from
DS90C3202. When DS90C3202 acknowledges (the 1st ACK) that the master is calling, the master then sends
the data register address byte and waits for acknowledge from the slave. When the slave acknowledges (the 2nd
ACK), the master sends the data byte and wait for acknowledge from the slave. When the slave acknowledges
(the 3rd ACK), the master generates a “ Stop”. This completes the “WRITE”.
DS90C3202 Two-Wire Serial Interface Register Table
Address
R/W
RESET
0d/0h
R
PWDN
1d/1h
R
PWDN
2d/2h
R
PWDN
3d/3h
R
PWDN
4d/4h
R
PWDN
5d/5h
R
PWDN
6d/6h
R
PWDN
7d/7h
R
PWDN
8d/8h
R
PWDN
9d/9h
R
PWDN
10d/ah
R
PWDN
11d/bh
R
PWDN
20d/14h
R/W
None
21d/15h
R/W
None
22d/16h
R/W
None
23d/17h
R/W
None
24d/18h
R/W
None
25d/19h
R/W
None
Bit #
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:3]
[2:0]
[7]
[6:4]
[3]
[2:0]
[7]
[6:4]
[3]
[2:0]
[7]
[6:4]
[3]
[2:0]
Description
Vender ID low byte[7:0] = 05h
Vender ID high byte[15:8] =13h
Device ID low byte[7:0] = 28h
Device ID high byte 15:8] = 67h
Device revision [7:0] = 00h to begin with
Low frequency limit, 8Mhz = 8h
High frequency limit 135Mhz = 87h =
0000_0000_1000_0111
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
LVDS input skew control for CLK channel,
000 (default) applies to no delay added, ONE buffer delay
per step adjustment towards Tsetup improvement
Reserved
LVDS input skew control for RXO channel B,
000 (default) applies to no delay added, ONE buffer delay
per step adjustment towards Thold improvements
Reserved
LVDS input skew control for RXO channel C,
000 (default) applies to no delay added, ONE buffer delay
per step adjustment towards Thold improvements
Reserved
LVDS input skew control for RXO channel D,
000 (default) applies to no delay added, ONE buffer delay
per step adjustment towards Thold improvements
Reserved
LVDS input skew control for RXO channel E,
000 (default) applies to no delay added, ONE buffer delay
per step adjustment towards Thold improvements
Reserved
LVDS input skew control for RXO channel A,
000 (default) applies to no delay added, ONE buffer delay
per step adjustment towards Thold improvements
Reserved
LVDS input skew control for RXE channel A,
000 (default) applies to no delay added, ONE buffer delay
per step adjustment towards Thold improvements
Default Value
0000_0101
0001_0011
0010_1000
0110_0111
0000_0000
0000_1000
1000_0111
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
20
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