DS90C3202_13 Datasheet, PDF (6/26 Pages) Texas Instruments – 3.3V 8 MHz to 135 MHz Dual FPD-Link Receiver

DS90C3202
SNLS191D – APRIL 2005 – REVISED APRIL 2013
www.ti.com
Receiver Switching Characteristics⁽¹⁾
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Condition or
Min
Typ
Max
Unit
Reference
CLHT
LVCMOS/LVTTL Low-to-High Transition Time, C_L
= 8pF, (Figure 7) ⁽²⁾
Register addr 28d/1ch,
bit [2] (RCLK)=0b (Default),
bit [1] (RXE) =0b (Default),
bit [0] (RXO) =0b (Default)
Rx clock out
Rx data out
1.45
2.10
ns
2.40
3.50
ns
CHLT
LVCMOS/LVTTL High-to-Low Transition Time, C_L
= 8pF, (Figure 7) ⁽²⁾
Register addr 28d/1ch,
bit [2] (RCLK)=0b (Default),
bit [1] (RXE) =0b (Default),
bit [0] (RXO) =0b (Default)
Rx clock out
Rx data out
1.35
2.20
ns
2.40
3.60
ns
CLHT
Programmable
adjustment
LVCMOS/LVTTL Low-to-High Transition Time, C_L
= 8pF, (Figure 7) ⁽²⁾
Register addr 28d/1ch,
bit [2] (RCLK)=1b (Default),
bit [1] (RXE) =1b (Default),
bit [0] (RXO) =1b (Default)
Rx clock out
Rx data out
2.45
ns
3.40
ns
CHLT
Programmable
adjustment
RCOP
LVCMOS/LVTTL High-to-Low Transition Time, C_L
= 8pF, (Figure 7) ⁽²⁾
Register addr 28d/1ch,
bit [2] (RCLK)=0b (Default),
bit [1] (RXE) =0b (Default),
bit [0] (RXO) =0b (Default)
RCLK OUT Period (Figure 13, Figure 14) ⁽²⁾
Rx clock out
Rx data out
8–135 MHz
2.35
ns
3.40
ns
7.4
T
125
ns
RCOH
RCLK OUT High Time (Figure 13 , Figure 14)
Rx clock out
0.4T
0.5T
0.6T
ns
RCOL
RSRC
RHRC
RSRC/RHRC
Programmable
Adjustment
RCLK OUT Low Time (Figure 13 , Figure 14)
Rx clock out
RxOUT Setup to RCLK OUT (Figure 13, Figure 14) ^{(2) (3)}
Register addr 29d/1dh [2:1]= 00b (Default)
RxOUT Hold to RCLK OUT (Figure 13 , Figure 14) ^{(2) (3)}
Register addr 29d/1dh [2:1]= 00b (Default)
Register addr 29d/1dh [2:1] = 01b, (Figure 15, Figure 16) ⁽⁴⁾
RSRC increased from default by 1UI
RHRC decreased from default by 1UI
Register addr 29d/1dh [2:1] = 10b, (Figure 15 Figure 16) ⁽⁴⁾
RSRC decreased from default by 1UI
RHRC increased from default by 1UI
Register addr 29d/1dh [2:1] = 11b, (Figure 15 Figure 16) ⁽⁴⁾
RSRC increased from default by 2UI
RHRC decreased from default by 2UI
0.4T
0.5T
0.6T
ns
2.60
0.5T
ns
3.60
0.5T
ns
+1UI / -1UI
ns
-1UI / +1UI
ns
+2UI / -2UI
ns
RPLLS
Receiver Phase Lock Loop Set (Figure 8)
10
ms
RPDD
Receiver Powerdown Delay (Figure 9)
100
ns
RPDL
Receiver Propagation Delay — Latency (Figure 10)
4*RCLK
ns
RITOL
Receiver Input Tolerance
(Figure 12 Figure 18) ^{(2) (4)}
V_CM = 1.25V,
V_ID = 350mV
0.25
UI
(1) Typical values are given for V_DD = 3.3V and T _A = +25°C.
(2) Specification is ensured by characterization.
(3) A Clock Unit Symbol (T) is defined as 1/ (Line rate of RCLK). E.g. For Line rate of RCLK at 85MHz, 1 T = 11.76ns
(4) A Unit Interval (UI) is defined as 1/7th of an ideal clock period (RCLK/7). E.g. For an 11.76ns clock period (85MHz), 1 UI = 1.68ns
6
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