DS90C3202_13 Datasheet, PDF (3/26 Pages) Texas Instruments – 3.3V 8 MHz to 135 MHz Dual FPD-Link Receiver

DS90C3202
www.ti.com
SNLS191D – APRIL 2005 – REVISED APRIL 2013
2 channels of video data (10-bit each for RGB for each channel, totaling 60 bits) and control signals (HSYNC,
VSYNC, DE and two user-defined signals) along with clock signal. The dual high speed LVDS channels supports
single pixel in-single pixel out and dual pixel in-dual pixel out transmission modes. The FPD-Link chipset is
suitable for a variety of display applications including LCD Monitors, LCD TV, Digital TV, and DLP TV, and
Plasma Display Panels.
Using a true 10-bit color depth system, the 30-bit RGB color produces over 1.07 billion colors to represent High
Definition (HD) displays in their most natural color, surpassing the maximum 16.7 million colors achieved by 6/8-
bit color conventionally used for large-scale LCD televisions and LCD monitors.
LVDS RECEIVER
The LVDS Receiver receives input RGB video data and control signal timing.
SELECTABLE OUTPUT DATA STROBE
The Receiver output data edge strobe can be latched on the rising or falling edges of clock signal. The dedicated
RFB pin is used to program output strobe select on the rising edge of RCLK or the falling edge of RCLK.
2-WIRE SERIAL COMMUNICATION INTERFACE
Optional Two-Wire serial interface programming allows fine tuning in development and production environments.
The Two-Wire serial interface provides several capabilities to reduce EMI and to customize output timing. These
capabilities are selectable/programmable via Two-Wire serial interface: Programmable Skew Rates, Progress
Turn On Function, Input/Output Channel Control.
PROGRAMMABLE SKEW RATES
Programmable edge rates allow the LVCMOS/LVTTL Data and Clock outputs to be adjusted for better
impedance matching for noise and EMI reduction. The individual output drive control registers for Rx data out
and Rx clock out are programmable via Two-Wire serial interface.
PROGRESS TURN ON FUNCTION
Progress Turn On (PTO) function aligns the two output channels of LVCMOS/LVTLL in either a non-skew data
format (simultaneous switching) or a skewed data format (staggered). The skewed format delays the selected
channel data and staggers the outputs. This reduces the number of outputs switching simultaneously, which
lowers EMI radiation and minimizes ground bounce. Feature is controlled via Two-Wire serial interface.
INPUT/OUTPUT CHANNEL CONTROL
Full independent control for input/output channels can be disabled to minimize power supply line noise and
overall power dissipation. Feature is configured via Two-Wire serial interface
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