DS90C3202_13 Datasheet, PDF (18/26 Pages) Texas Instruments – 3.3V 8 MHz to 135 MHz Dual FPD-Link Receiver

DS90C3202
SNLS191D – APRIL 2005 – REVISED APRIL 2013
www.ti.com
Pin No.
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
Pin Name
MODE1
VSSL
VDDL
RXOA-
RXOA+
RXOB-
RXOB+
RXOC-
RXOC+
RXOD-
RXOD+
RXOE-
RXOE+
VSSL
VSSL
VDDL
VDDL
RCLKIN-
RCLKIN+
RXEA-
RXEA+
RXEB-
RXEB+
RXEC-
RXEC+
RXED-
RXED+
RXEE-
RXEE+
MODE0
RFB
DS90C3202 PIN DESCRIPTIONS (continued)
I/O
Pin Type
I/P
Digital (pulldown)
GND
VDD
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
GND
GND
VDD
VDD
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
LVDS PWR
LVDS PWR
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS PWR
LVDS PWR
LVDS PWR
LVDS PWR
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
Digital (pulldown)
I/P
Digital (pulldown)
Description
“ODD” Bank Enable
0 = LVTTL ODD OUTPUTS DISABLED
(Data Output Low)
1 = LVTTL ODD OUTPUTS ENABLED
Ground pin for LVDS
Power supply pin for LVDS
Negative LVDS differential data input
Positive LVDS differential data input
Negative LVDS differential data input
Positive LVDS differential data input
Negative LVDS differential data input
Positive LVDS differential data input
Negative LVDS differential data input
Positive LVDS differential data input
Negative LVDS differential data input
Positive LVDS differential data input
Ground pin for LVDS
Ground pin for LVDS
Power supply pin for LVDS
Power supply pin for LVDS
Negative LVDS differential clock input
Positive LVDS differential clock input
Negative LVDS differential data input
Positive LVDS differential data input
Negative LVDS differential data input
Positive LVDS differential data input
Negative LVDS differential data input
Positive LVDS differential data input
Negative LVDS differential data input
Positive LVDS differential data input
Negative LVDS differential data input
Positive LVDS differential data input
“EVEN” Bank Enable
0 = LVTTL EVEN OUTPUTS DISABLED
(Data Output Low)
1 = LVTTL EVEN OUTPUTS ENABLED
Rising Falling Bar (Figure 11)
0 = FALLING EDGE DATA STROBE
1 = RISING EDGE DATA STROBE
18
Submit Documentation Feedback
Product Folder Links: DS90C3202
Copyright © 2005–2013, Texas Instruments Incorporated