DS50PCI401_13 Datasheet, PDF(8/36 Page) Texas Instruments – DS50PCI401 2.5 Gbps / 5.0 Gbps 4 Lane PCI Express Repeater with Equalization and De-Emphasis

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

DS50PCI401_13 Datasheet, PDF (8/36 Pages) Texas Instruments – DS50PCI401 2.5 Gbps / 5.0 Gbps 4 Lane PCI Express Repeater with Equalization and De-Emphasis

◁

DS50PCI401

SNLS292J â JUNE 2009 â REVISED APRIL 2013

www.ti.com

PRSNT#

Table 6. Receiver Detect Pins for A and B ports (LVCMOS inputs) (continued)

ENRXDET

RXDETA/B

Function

Power down mode: Input termination 50Î©. Associated output channels off. Part in power

saving mode.

USING RXDETA/B IN A PCIe ENVIRONMENT

In order for upstream and downstream PCIe subsystems to communicate in a cabling environment, the PCIe

specification includes several auxiliary or sideband signals to manage system-level functionality or

implementation. Similar methods are used in backplane applications, but the exact implementation falls outside

the PCIe standard. Initial communication from the downstream subsystem to the upstream subsystem is done

with the CPRSNT# auxiliary signal. The CPRSNT# signal is asserted Low by the downstream componentry after

the "Power Good" condition has been established. This mechanism allows for the upstream subsystem to

determine whether the power is good within the downstream subsystem, enable the reference clock, and initiate

the Link Training Sequence.

CPWRON

CPERST#

CPRSNT#

CREFCLK

CPRSNT# to RESET Removal

5 ms (min)

RESET Removed and

REFCLK Stable

Figure 2. Typical PCIe System Timing

The signals shown in the graphic could be easily replicated within the downstream subsystem and used to

control the RXDETA/B inputs on the DS50PCI401. Often an onboard microcontroller will be used to handle

events like power-up, power-down, power saving modes, and hot insertion. The microcontroller would use the

same information to determine when to enable and disable the DS50PCI401 input termination. In applications

that require SMBus control, the microcontroller could also delay any response to the upstream subsystem to

allow sufficient time to correctly program the DS50PCI401 and other devices on the board.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Submit Documentation Feedback

Product Folder Links: DS50PCI401

▷