DS50PCI401_13 Datasheet, PDF (4/36 Pages) Texas Instruments – DS50PCI401 2.5 Gbps / 5.0 Gbps 4 Lane PCI Express Repeater with Equalization and De-Emphasis

DS50PCI401
SNLS292J – JUNE 2009 – REVISED APRIL 2013
Pin Name
Pin Number
Differential High Speed I/O's
IA_0+, IA_0- ,
IA_1+, IA_1-,
IA_2+, IA_2-,
IA_3+, IA_3-
10, 11
12, 13
15, 16
17, 18
OA_0+, OA_0-,
OA_1+, OA_1-,
OA_2+, OA_2-,
OA_3+, OA_3-
35, 34
33, 32
31, 30
29, 28
IB_0+, IB_0- ,
IB_1+, IB_1-,
IB_2+, IB_2-,
IB_3+, IB_3-
45, 44
43, 42
40, 39
38, 37
OB_0+, OB_0-,
1, 2
OB_1+, OB_1-,
3, 4
OB_2+, OB_2-,
5, 6
OB_3+, OB_3-
7, 8
Control Pins — Shared (LVCMOS)
ENSMB
48
ENSMB = 1 (SMBUS MODE)
SCL
50
SDA
49
AD0-AD3
54, 53, 47, 46
ENSMB = 0 (NORMAL PIN MODE)
EQA0, EQA1
EQB0, EQB1
20, 19
46, 47
DEMA0, DEMA1
DEMB0, DEMB1
49, 50
53, 54
RATE
21
Table 1. Pin Descriptions
I/O, Type
Pin Description
www.ti.com
I, CML
O,LPDS
I, CML
O,LPDS
Inverting and non-inverting CML differential inputs to the equalizer. A
gated on-chip 50Ω termination resistor connects INA_0+ to VDD and
INA_0- to VDD when enabled.
Inverting and non-inverting low power differential signal (LPDS) 50Ω
driver outputs with de-emphasis. Compatible with AC coupled CML
inputs.
Inverting and non-inverting CML differential inputs to the equalizer. A
gated on-chip 50Ω termination resistor connects INB_0+ to VDD and
INB_0- to VDD when enabled.
Inverting and non-inverting low power differential signal (LPDS) 50Ω
driver outputs with de-emphasis. Compatible with AC coupled CML
inputs.
I, LVCMOS
w/internal
pulldown
System Management Bus (SMBus) enable pin.
When pulled high provide access internal digital registers that are a
means of auxiliary control for such functions as equalization, de-
emphasis, VOD, rate, and idle detection threshold.
When pulled low, access to the SMBus registers are disabled and
SMBus function pins are used to control the Equalizer and De-Emphasis.
Please refer to SYSTEM MANAGEMENT BUS (SMBUS) AND
CONFIGURATION REGISTERS and Electrical Characteristics — Serial
Management Bus Interface for detail information.
I, LVCMOS
I, LVCMOS,
O, Open Drain
I, LVCMOS
w/internal
pulldown
ENSMB = 1
SMBUS clock input pin is enabled. External pull-up resistor maybe
needed. Refer to R_TERM in the SMBus specification.
ENSMB = 1
The SMBus bi-directional SDA pin is enabled. Data input or open drain
output. External pull-up resistor is required.
Refer to R_TERM in the SMBus specification.
ENSMB = 1
SMBus Slave Address Inputs. In SMBus mode, these pins are the user
set SMBus slave address inputs. See section — SYSTEM
MANAGEMENT BUS (SMBUS) AND CONFIGURATION REGISTERS
for additional information.
I,FLOAT,
LVCMOS
I,FLOAT,
LVCMOS
I,FLOAT,
LVCMOS
EQA/B ,0/1 controls the level of equalization of the A/B sides as shown in
Table 2. The EQA/B pins are active only when ENSMB is de-asserted
(Low). Each of the 4 A/B channels have the same level unless controlled
by the SMBus control registers. When ENSMB goes high the SMBus
registers provide independent control of each lane, and the EQB0/B1
pins are converted to SMBUS AD2/AD3 inputs.
DEMA/B ,0/1 controls the level of de-emphasis of the A/B sides as
shown in Table 3. The DEMA/B pins are only active when ENSMB is de-
asserted (Low). Each of the 4 A/B channels have the same level unless
controlled by the SMBus control registers. When ENSMB goes High the
SMBus registers provide independent control of each lane and the DEM
pins are converted to SMBUS AD0/AD1 and SCL/SDA inputs.
RATE control pin controls the pulse width of de-emphasis of the output.
A Low forces Gen1 (2.5Gbps), High forces Gen 2 (5Gbps),
Open/Floating the rate is internally detected after each exit from idle and
the pulse width is set appropriately. When ENSMBUS= 1 this pin is
disabled and the RATE function is controlled internally by the SMBUS
registers. Refer to Table 3.
4
Submit Documentation Feedback
Product Folder Links: DS50PCI401
Copyright © 2009–2013, Texas Instruments Incorporated