DS50PCI401_13 Datasheet, PDF (10/36 Pages) Texas Instruments – DS50PCI401 2.5 Gbps / 5.0 Gbps 4 Lane PCI Express Repeater with Equalization and De-Emphasis

DS50PCI401
SNLS292J – JUNE 2009 – REVISED APRIL 2013
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Electrical Characteristics
Over recommended operating supply and temperature ranges with default register settings unless other specified. ^{(1) (2)}
Symbol
POWER ⁽³⁾
Parameter
Conditions
Min
Typ
Max
Units
PD
Power Dissipation
EQX=Float, DEX=0, VOD=1Vpp
,PRSNT=0
758
950
mW
PRSNT=1, ENSMB=0
0.92
1.125
mW
LVCMOS / LVTTL DC SPECIFICATIONS
V_IH
High Level Input
(4)
Voltage
V_IL
Low Level Input
(4)
Voltage
2
3.6
V
0
0.8
V
V_OH
High Level Output
SMBUS open drain V_OH set by
Voltage
pullup Resistor
V
V_OL
Low Level Output
I_OL = 4mA
Voltage
0.4
V
I_IH
Input High Current
V_IN = 3.6V , LVCMOS
-15
+15
V_IN = 3.6V , w/
-15
FLOAT,PULLDOWN input
+120
μA
I_IL
Input Low Current
CML RECEIVER INPUTS (IN_n+, IN_n-)
RL_RX-DIFF
Rx package plus Si
differential return loss
RL_RX-CM
Common mode Rx
return loss
V_IN = 0V
V_IN = 0V, w/FLOAT input
0.05GHz – 1.25GHz ⁽⁵⁾
1.25GHz – 2.5GHz ⁽⁵⁾
0.05GHz - 2.5GHz ⁽⁵⁾
-15
+15
μA
-80
+15
-21
dB
-20
-11.5
dB
Z_RX-DC
Rx DC common mode Tested at VDD=0
impedance
40
50
60
Ω
Z_RX-DIFF-DC
Rx DC differential
impedance
Tested at VDD=0
85
100
115
Ω
V_RX-DIFF-DC
Differential Rx peak to Tested at DC, TXIDLEx=0
peak voltage
0.10
1.2
V
Z_{RX-HIGH-IMP-DC -POS}
DC Input CM
Vin = 0 to 200 mV,
impedance for V>0
RXDETA/B = 0,
50
KΩ
ENSMB = 0, VDD=2.625
V_{RX-IDLE-DET-DIFF-PP}
Electrical Idle detect
threshold
SD_TH = float, see Table 5,
(6)
40
175
mV_P-P
LPDS OUTPUTS (OUT_n+, OUT_n-)
V_TX-DIFF-PP
Output Voltage Swing Differential measurement with
OUT_n+ and OUT_n- terminated
by 50Ω to GND AC-Coupled,
800
1000
1200
mV_P-P
Figure 4, ⁽³⁾
V_OCM
Output Common-Mode Single-ended measurement DC-
Voltage
Coupled with 50Ω termination, ⁽¹⁾
V_DD - 1.4
V
V_{TX-DE-RATIO-3.5}
Tx de-emphasis level VOD = 1000 mV, DEM1 = GND,
ratio
DEM0 = VDD, ⁽¹⁾, ⁽⁷⁾
3.5
dB
(1) Typical values represent most likely parametric norms at V_DD = 2.5V, T_A = 25°C., and at the Recommended Operation Conditions at the
time of product characterization and are not guaranteed.
(2) The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not guaranteed.
(3) Measured with DEM Select pins configured for 1000mV VOD, see De-emphasis table.
(4) Input edge rate for LVCMOS/FLOAT inputs must be 50ns minimum from 10-90%.
(5) Input Return Loss also uses the setup shown in Figure 6. The blocking / biasing circuit is replaced with a simple AC coupling capacitor
for each input to emulate a typical PCIe application.
(6) Measured at package pins of receiver. Less than 40mV is IDLE, greater than 175mV is ACTIVE. SD_TH pin connected with resistor to
GND overrides this default setting.
(7) Measured with a repeating K28.5 pattern at a data rate of 2.5 Gbps and 5.0 Gbps.
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