DS50PCI401_13 Datasheet, PDF (18/36 Pages) Texas Instruments – DS50PCI401 2.5 Gbps / 5.0 Gbps 4 Lane PCI Express Repeater with Equalization and De-Emphasis

DS50PCI401
SNLS292J – JUNE 2009 – REVISED APRIL 2013
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pin 46 – CH4 with CH6,
pin 47 – CH5 with CH7.
Pin = HIGH (VDD) means IDLE is detected (no signal present).
Pin = LOW (GND) means ACTIVE (data signal present).
To monitor the RATE detect with two channels ORed (CH0 with CH2, CH1 with CH3, CH4 with CH6, CH5 with
CH7):
Write C0'h to address 0x4C.
The following RATE status should be observable on the external pins:
pin 19 – CH0 with CH2,
pin 20 – CH1 with CH3,
pin 46 – CH4 with CH6,
pin 47 – CH5 with CH7.
Pin = HIGH (VDD) means high data rate is detected (6 Gbps).
Pin = LOW (GND) means low rate is detected (3 Gbps).
Address Register Name
0x00
Reset
0x01
PWDN Channels
0x02
PWDN Control
0x08
Pin Control Override
0x0E
CH0 - CHB0
IDLE RATE Select
Table 7. SMBus Register Map
Bit (s) Field
7:1 Reserved
0
Reset
7:0 PWDN CHx
7:1 Reserved
0
Override PWDN
7:5 Reserved
4
Override IDLE
3
Reserved
2
Override RATE
1:0 Reserved
7:6 Reserved
5
IDLE auto
4
IDLE select
3:2 Reserved
1
RATE auto
0
RATE select
Type
R/W
R/W
R/W
R/W
R/W
Default
0x00
0x00
0x00
0x00
0x00
Description
Set bits to 0.
SMBus Reset
1: Reset registers to default value
Power Down per Channel
[7]: CHA_3
[6]: CHA_2
[5]: CHA_1
[4]: CHA_0
[3]: CHB_3
[2]: CHB_2
[1]: CHB_1
[0]: CHB_0
00'h = all channels enabled
FF'h = all channels disabled
Set bits to 0.
0: Allow PWDN pin control
1: Block PWDN pin control
Set bits to 0.
0: Allow IDLE pin control
1: Block IDLE pin control
Set bit to 0.
0: Allow RATE pin control
1: Block RATE pin control
Set bits to 0.
Set bits to 0.
0: Allow IDLE_sel control in Bit 4
1: Automatic IDLE detect
0: Output is ON (SD is disabled)
1: Output is muted (electrical idle)
Set bits to 0.
0: Allow RATE_sel control in Bit 0
1: Automatic RATE detect
0: 2.5 Gbps
1: 5.0 Gbps
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