DS50PCI401_13 Datasheet, PDF (17/36 Pages) Texas Instruments – DS50PCI401 2.5 Gbps / 5.0 Gbps 4 Lane PCI Express Repeater with Equalization and De-Emphasis

DS50PCI401
www.ti.com
SNLS292J – JUNE 2009 – REVISED APRIL 2013
6. The Host drives the 7-bit SMBus Address, and a “1” indicating a READ.
7. The Device drives an ACK bit “0”.
8. The Device drives the 8-bit data value (register contents).
9. The Host drives a NACK bit “1”indicating end of the READ transfer.
10. The Host drives a STOP condition.
The READ transaction is completed, the bus goes IDLE and communication with other SMBus devices may now
occur.
Please see Table 7 for more information.
SMBus REGISTER WRITES:
The DS50PCI401 outputs will NOT be PCIe compliant with the SMBus registers enabled (ENSMB = 1) until the
VOD levels have been set. Below is an example to configure the VOD level to a PCIe compliant amplitude and
adjust the DE and EQ signal conditioning to work with a 7m PCIe cable interconnect on the input B-side / output
A-side of the device
1. Reset the SMBus registers to default values:
– Write 01'h to address 0x00.
2. Set VOD = 1.0V for all channels (OA[3:0] and OB[3:0]):
– Write 0F'h to address 0x10, 0x17, 0x1E, 0x25, 0x2D, 0x34, 0x3B, 0x42.
3. Set equalization to external pin level EQ[1:0] = 10 (~15.5 dB at 2.5 GHz) for all channels (IB[3:0]):
– Write 39'h to address 0x0F, 0x16, 0x1D, 0x24.
4. Set de-emphasis to DE[1:0] = F1 or -12 dB enhanced for all A channels (OA[3:0]):
– Write A0'h to address 0x2E, 0x35, 0x3C, 0x43.
IDLE AND RATE DETECTION TO EXTERNAL PINS
The functions of IDLE and RATE detection to external pins for monitoring can be supported in SMBus mode. The
external GPIO pins of 19, 20, 46 and 47 will be changed and they will serve as outputs for IDLE and RATE
detect signals.
The following external pins should be set to auto detection:
RATE = F (FLOAT) – auto RATE detect enabled
TXIDLEA/B = F (FLOAT) – auto IDLE detect enabled
There are 4 GPIO pins that can be configured as outputs with reg_4E[0].
To disable the external SMBus address pins, so pin 46 and 47 can be used as outputs:
Write 01'h to address 0x4E.
Care must be taken to ensure that only the desired status block is enabled and attached to the external pin as
the status blocks can be OR’ed together internally. Register bits reg_47[5:4] and bits reg_4C[7:6] are used to
enable each of the status block outputs to the external pins. The channel status blocks can be internally OR’ed
together to monitor more than one channel at a time. This allows more information to be presented on the status
outputs and later if desired, a diagnosis of the channel identity can be made with additional SMBus writes to
register bits reg_47[5:4] and bits reg_4C[7:6].
Below are examples to configure the device and bring the internal IDLE and RATE status to pins 19, 20, 46, 47.
To monitor the IDLE detect with two channels ORed (CH0 with CH2, CH1 with CH3, CH4 with CH6, CH5 with
CH7):
Write 32'h to address 0x47.
The following IDLE status should be observable on the external pins:
pin 19 – CH0 with CH2,
pin 20 – CH1 with CH3,
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