DS100KR401_13 Datasheet, PDF (8/38 Pages) Texas Instruments – Ultra Low Power, 4 Lane (8-channel, bi-directional) Repeater for Data-rates up to 10.3 Gbps

DS100KR401
SNLS395B – JANUARY 2012 – REVISED MARCH 2012
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ELECTRICAL CHARACTERISTICS — SERIAL MANAGEMENT BUS INTERFACE (continued)
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Min
Typ
Max Units
TSU:STO
Stop Condition Setup Time
0.6
µs
THD:DAT
Data Hold Time
0
ns
TSU:DAT
Data Setup Time
100
ns
T_LOW
T_HIGH
t_F
t_R
t_POR
Clock Low Period
Clock High Period
Clock/Data Fall Time
Clock/Data Rise Time
Time in which a device must be
operational after power-on reset
See ⁽⁴⁾
See ⁽⁴⁾
See ⁽⁴⁾
See ^{(4) (5)}
1.3
µs
0.6
50
µs
300
ns
300
ns
500
ms
(4) Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1
SMBus common AC specifications for details.
(5) Specified by Design. Parameter not tested in production.
TIMING DIAGRAMS
(OUT+)
V_OD (p-p) = (OUT+) ± (OUT-)
(OUT-)
80%
0V
20%
t_RISE
80%
20%
t_FALL
Figure 2. CML Output and Rise and FALL Transition Time
+
IN
0V
-
t_PLHD
+
OUT
0V
-
t_PHLD
Figure 3. Propagation Delay Timing Diagram
t_LOW
t_R
t_BUF
t_HD:STA
t_HD:DAT
t_HIGH
t_F
t_SU:DAT
t_SU:STA
t_SU:STO
SP
ST
ST
SP
Figure 4. SMBus Timing Parameters
SCL
SDA
8
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