DS100KR401_13 Datasheet, PDF (4/38 Pages) Texas Instruments – Ultra Low Power, 4 Lane (8-channel, bi-directional) Repeater for Data-rates up to 10.3 Gbps

DS100KR401
SNLS395B – JANUARY 2012 – REVISED MARCH 2012
www.ti.com
Pin Name
Pin Number
Differential High Speed I/O's
OUT_B_0+, OUT_B_0- 1, 2,
,
3, 4,
OUT_B_1+, OUT_B_1- 5, 6,
,
7, 8
OUT_B_2+, OUT_B_2-
,
OUT_B_3+, OUT_B_3-
IN_A_0+, IN_A_0-,
IN_A_1+, IN_A_1-,
IN_A_2+, IN_A_2-,
IN_A_3+, IN_A_3-
10, 11,
12, 13,
15, 16,
17, 18
IN_B_0+, IN_B_0-,
IN_B_1+, IN_B_1-,
IN_B_2+, IN_B_2-,
IN_B_3+, IN_B_3-
45, 44,
43, 42,
40, 39,
38, 37
OUT_A_0+, OUT_A_0- 35, 34,
,
33, 32,
OUT_A_1+, OUT_A_1- 31, 30,
,
29, 28
OUT_A_2+, OUT_A_2-
,
OUT_A_3+, OUT_A_3-
Control Pins — Shared (LVCMOS)
ENSMB
48
ENSMB = 1 (SMBUS MODE)
SCL
50
SDA
49
AD0-AD3
54, 53, 47, 46
READ_EN
26
ENSMB = 0 (PIN MODE)
EQA0, EQA1,
EQB0, EQB1
20, 19, 46, 47
DEMA0, DEMA1,
DEMB0, DEMB1
49, 50, 53, 54
PIN DESCRIPTIONS⁽¹⁾
I/O, Type
Pin Description
O
Inverting and non-inverting 50Ω driver bank B outputs with de-emphasis.
Compatible with AC coupled CML inputs.
I
Inverting and non-inverting differential inputs to bank A equalizer. A gated on-
chip 50Ω termination resistor connects INA_n+ to VDD and INA_n- to VDD
when enabled.
I
Inverting and non-inverting differential inputs to bank B equalizer. A gated on-
chip 50Ω termination resistor connects INB_n+ to VDD and INB_n- to VDD
when enabled.
O
Inverting and non-inverting 50Ω driver bank A outputs with de-emphasis.
Compatible with AC coupled CML inputs.
I, LVCMOS
System Management Bus (SMBus) enable pin
Tie 1kΩ to VDD = Register Access SMBus Slave mode
FLOAT = Read External EEPROM (Master SMBUS Mode)
Tie 1kΩ to GND = Pin Mode
I, LVCMOS,
O, OPEN
Drain
I, LVCMOS,
O, OPEN
Drain
I, LVCMOS
I, 4-LEVEL,
LVCMOS
ENSMB Master or Slave mode
SMBUS clock input pin is enabled.
Clock output when loading EEPROM configuration (master mode).
ENSMB Master or Slave mode
The SMBus bi-directional SDA pin is enabled. Data input or open drain (pull-
down only) output.
ENSMB Master or Slave mode
SMBus Slave Address Inputs. In SMBus mode, these pins are the user set
SMBus slave address inputs.
When using an External EEPROM, a transition from high to low starts the
load from the external EEPROM
I, 4-LEVEL,
LVCMOS
I, 4-LEVEL,
LVCMOS
EQA[1:0] and EQB[1:0] control the level of equalization on the input pins. The
pins are active only when ENSMB is deasserted (low). The 8 channels are
organized into two banks. Bank A is controlled with the EQA[1:0] pins and
bank B is controlled with the EQB[1:0] pins. When ENSMB is high the SMBus
registers provide independent control of each channel. The EQB[1:0] pins are
converted to SMBUS AD2/ AD3 inputs.
See Table 2
DEMA[1:0] and DEMB[1:0] control the level of de-emphasis of the output
driver when in Gen1/2 mode. The pins are only active when ENSMB is de-
asserted (low). The 8 channels are organized into two banks. Bank A is
controlled with the DEMA [1:0] pins and bank B is controlled with the
DEMB[1:0] pins. When ENSMB is high the SMBus registers provide
independent control of each channel. The DEMA[1:0] pins are converted to
SMBUS SCL/SDA and DEMB[1:0] pins are converted to AD0, AD1 inputs.
See Table 3
(1) Notes:
LVCMOS inputs without the “Float” conditions must be driven to a logic low or high at all times or operation is not guaranteed.
Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.
For 3.3V mode operation, VIN pin = 3.3V and the "VDD" for the 4-level input is 3.3V.
For 2.5V mode operation, VDD pin = 2.5V and the "VDD" for the 4-level input is 2.5V.
4
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