DS100KR401_13 Datasheet, PDF (7/38 Pages) Texas Instruments – Ultra Low Power, 4 Lane (8-channel, bi-directional) Repeater for Data-rates up to 10.3 Gbps

DS100KR401
www.ti.com
SNLS395B – JANUARY 2012 – REVISED MARCH 2012
ELECTRICAL CHARACTERISTICS⁽¹⁾ (continued)
Symbol
Parameter
Conditions
Min Typ⁽²⁾ Max Units
T_TX-RISE-FALL
T_RF-MISMATCH
RL_TX-DIFF
Transmitter rise/fall time
Transmitter rise/fall mismatch
Differential return loss
20% to 80% of differential output voltage
20% to 80% of differential output voltage
0.05 GHz - 7.5 GHz
7.5 GHz - 15 GHz
35
45
ps
0.01 0.1
UI
-15
dB
-5
dB
RL_TX-CM
Z_TX-DIFF-DC
V_TX-CM-AC-PP
I_TX-SHORT
T_PDEQ
T_LSK
T_PPSK
Common mode return loss
DC differential TX impedance
TX AC common mode voltage
Transmitter short circuit current
limit
Differential propagation delay
Lane to lane skew
Part to part propagation delay
skew
0.05 GHz - 5 GHz
VOD = 1.0 Vp-p, DEM0 = 1, DEM1 = 0
Total current the transmitter can supply when
shorted to VDD or GND
EQ = 00, ⁽³⁾
T = 25C, VDD = 2.5V
T = 25C, VDD = 2.5V
-10
dB
100
Ω
100 mVpp
20
mA
200
ps
25
ps
40
ps
Equalization
DJE1
Residual deterministic jitter at
10.3 Gbps
35” 4 mil FR4, VID = 0.8 Vp-p, PRBS15,
EQ = 1F'h, DEM = 0 dB
0.3
UI
DJE2
Residual deterministic jitter at
10.3 Gbps
10 meters 30 awg cable, VID = 0.8 Vp-p,
PRBS15, EQ = 2F'h, DEM = 0 dB
0.3
UI
De-emphasis
DJD1
Residual deterministic jitter at
10.3 Gbps
20” 4mils FR4, VID = 0.8 Vp-p, PRBS15,
EQ = 00, VOD = 1.0 Vp-p, DEM = −9 dB
0.1
UI
(3) Propagation Delay measurements will change slightly based on the level of EQ selected. EQ = 00 will result in the shortest propagation
delays.
ELECTRICAL CHARACTERISTICS — SERIAL MANAGEMENT BUS INTERFACE
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Min
Typ
SERIAL BUS INTERFACE DC SPECIFICATIONS
V_IL
Data, Clock Input Low Voltage
V_IH
Data, Clock Input High Voltage
2.1
I_PULLUP
Current Through Pull-Up Resistor High Power Specification
or Current Source
4
V_DD
I_LEAK-Bus
I_LEAK-Pin
C_I
R_TERM
Nominal Bus Voltage
Input Leakage Per Bus Segment
Input Leakage Per Device Pin
Capacitance for SDA and SCL
External Termination Resistance
pull to V_DD = 2.5V ± 5%
OR 3.3V ± 10%
See ⁽¹⁾
See ^{(1) (2)}
Pullup V_DD = 3.3V, See ^{(1) (2) (3)}
Pullup V_DD = 2.5V, See ^{(1) (2) (3)}
2.375
-200
-15
2000
1000
SERIAL BUS INTERFACE TIMING SPECIFICATIONS
FSMB
Bus Operating Frequency
ENSMB = VDD (Slave Mode)
ENSMB = FLOAT (Master Mode)
280
400
TBUF
Bus Free Time Between Stop and
Start Condition
1.3
THD:STA
Hold time after (Repeated) Start At I_PULLUP, Max
Condition. After this period, the
0.6
first clock is generated.
TSU:STA
Repeated Start Condition Setup
Time
0.6
Max
0.8
3.6
3.6
+200
10
400
520
Units
V
V
mA
V
µA
µA
pF
Ω
Ω
kHz
kHz
µs
µs
µs
(1) Recommended value.
(2) Recommended maximum capacitance load per bus segment is 400pF.
(3) Maximum termination voltage should be identical to the device supply voltage.
Copyright © 2012, Texas Instruments Incorporated
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