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DS100KR401_13 Datasheet, PDF (17/38 Pages) Texas Instruments – Ultra Low Power, 4 Lane (8-channel, bi-directional) Repeater for Data-rates up to 10.3 Gbps
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DS100KR401
www.ti.com
SNLS395B – JANUARY 2012 – REVISED MARCH 2012
Table 6. Example of EEPROM for 4 Devices Using 2 Address Maps(1) (continued)
EEPROM Address
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Address (Hex)
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
EEPROM Data
0x54
0x54
0x00
0x00
0x04
0x07
0x00
0x00
0xAB
0x00
0x00
0x0A
0xB0
0x00
0x00
0xAB
0x00
0x00
0x0A
0xB0
0x01
0x80
0x01
0x56
0x00
0x00
0x15
0x60
0x00
0x01
0x56
0x00
0x00
0x15
0x60
0x00
0x00
0x54
0x54
Comments
End Device 0, 1 - Address Offset 39
Begin Device 2, 3 - Address Offset 3
EQ CHB0 = 00
VOD CHB0 = 1.0V
DEM CHB0 = 0 (0dB)
EQ CHB1 = 00
VOD CHB1 = 1.0V
DEM CHB1 = 0 (0dB)
EQ CHB2 = 00
VOD CHB2 = 1.0V
DEM CHB2 = 0 (0dB)
EQ CHB3 = 00
VOD CHB3 = 1.0V
DEM CHB3 = 0 (0dB)
EQ CHA0 = 00
VOD CHA0 = 1.0V
DEM CHA0 = 0 (0dB)
EQ CHA1 = 00
VOD CHA1 = 1.0V
DEM CHA1 = 0 (0dB)
EQ CHA2 = 00
VOD CHA2 = 1.0V
DEM CHA2 = 0 (0dB)
EQ CHA3 = 00
VOD CHA3 = 1.0V
DEM CHA3 = 0 (0dB)
End Device 2, 3 - Address Offset 39
SYSTEM MANAGEMENT BUS (SMBus) and CONFIGURATION REGISTERS
The System Management Bus interface is compatible to SMBus 2.0 physical layer specification. ENSMB = 1kΩ
to VDD to enable SMBus slave mode and allow access to the configuration registers.
The DS100KR401 has the AD[3:0] inputs in SMBus mode. These pins are the user set SMBUS slave address
inputs. The AD[3:0] pins have internal pull-down. When left floating or pulled low the AD[3:0] = 0000'b, the device
default address byte is B0'h. Based on the SMBus 2.0 specification, the DS100KR401 has a 7-bit slave address.
The LSB is set to 0'b (for a WRITE). The device supports up to 16 address byte, which can be set with the
AD[3:0] inputs. Below are the 16 addresses.
Copyright © 2012, Texas Instruments Incorporated
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