DDC114IRTCT Datasheet, PDF (8/35 Pages) Texas Instruments – Quad Current Input, 20-Bit Analog-To-Digital Converter

DDC114
SBAS255C − JUNE 2004 − REVISED APRIL 2009
THEORY OF OPERATION
The block diagram of the DDC114 is shown in Figure 1.
The device contains four identical input channels that
perform the function of current-to-voltage integration
followed by a multiplexed A/D conversion. Each input has
two integrators so that the current-to-voltage integration
can be continuous in time. The output of the eight
integrators are switched to two delta-sigma (∆Σ)
converters via two four-input multiplexers. With the
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DDC114 in the continuous integration mode, the output of
the integrators from one side of both of the inputs will be
digitized while the other two integrators are in the
integration mode, as illustrated in the timing diagram in
Figure 2. This integration and A/D conversion process is
controlled by the system clock, CLK. The results from side
A and side B of each signal input are stored in a serial
output shift register. The DVALID output goes low when
the shift register contains valid data.
AVDD
VREF DVDD
IN1
Dual
Switched
Integrator
IN3
Dual
Switched
Integrator
IN2
Dual
Switched
Integrator
IN4
Dual
Switched
Integrator
AGND
∆Σ
Modulator
∆Σ
Modulator
Digital
Filter
Digital
Filter
Control
CLK
CONV
RANGE0
RANGE1
RANGE2
TEST
CLK_4X
HISPD/LOPWR
RESET
D ig ita l
Input/Output
FORMAT
DCLK
DCLK
DVALID
DOUT
DOUT
DIN
DIN
DGND
Figure 1. DDC114 Block Diagram
IN1 and IN2, Integrator A
Integrate
Integrate
IN1 and IN2, Integrator B
IN3 and IN4, Integrator A
Integrate
Integrate
Integrate
Integrate
IN3 and IN4, Integrator B
Integrate
Integrate
Conversion in Progress
IN1B
IN2B
IN3B
IN4B
IN1A
IN2A
IN3A
IN4A
IN1B
IN2B
IN3B
IN4B
IN1A
IN2A
IN3A
IN4A
DVALID
Figure 2. Basic Integration and Conversion Timing for the DDC114 (continuous mode)
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