DDC114IRTCT Datasheet, PDF (14/35 Pages) Texas Instruments – Quad Current Input, 20-Bit Analog-To-Digital Converter

DDC114
SBAS255C − JUNE 2004 − REVISED APRIL 2009
Conversion Rate
The conversion rate of the DDC114 is set by a combination
of the integration time (determined by the user) and the
speed of the A/D conversion process. The A/D conversion
time is primarily a function of the system clock (CLK)
speed. One A/D conversion cycle encompasses the
conversion of two signals (one side of each dual integrator
feeding the modulator) and the reset time for each of the
integrators involved in the two conversions. In most
situations, the A/D conversion time is shorter than the
integration time. If this condition exists, the DDC114 will
operate in continuous mode. When the DDC114 is in
continuous mode, the sensor output is continuously
integrated by one of the two sides of each input.
In the event that the A/D conversion takes longer than the
integration time, the DDC114 will switch into a
non-continuous mode. In non-continuous mode, the A/D
converter is not able to keep pace with the speed of the
integration process. Consequently, the integration
process is periodically halted until the digitizing process
catches up. These two basic modes of operation for the
DDC114—continuous and non-continuous modes—are
described below.
Continuous and Non-Continuous Operational
Modes
Figure 10 shows the state diagram of the DDC114. In all,
there are eight states. Table 5 provides a brief explanation
of each state.
STATE
1
2
3
4
5
6
7
8
Table 5. State Descriptions
MODE
Ncont
Ncont
Cont
Cont
Cont
Cont
Ncont
Ncont
DESCRIPTION
Complete m/r/az of side A, then side B (if previous
state is state 4). Initial power-up state when CONV
is initially held HIGH.
Prepare side A for integration.
Integrate on side A.
Integrate on side B; m/r/az on side A.
Integrate on side A; m/r/az on side B.
Integrate on side B.
Prepare side B for integration.
Complete m/r/az of side B, then side A (if previous
state is state 5). Initial power-up state when CONV
is initially held LOW.
Four signals are used to control progression around the
state diagram: CONV, mbsy, and their complements. The
state machine uses the level as opposed to the edges of
CONV to control the progression. mbsy is an internally-
generated signal not available to the user. It is active
whenever a measurement/reset/auto-zero (m/r/az) cycle
is in progress.
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CONV|mbsy
1
Ncont
CONV × mbsy
2
Ncont
CONV × mbsy
CONV
3
Int A
Cont
CONV
4
Int B/Meas A
Cont
CONV × mbsy
CONV × mbsy
5
Int A/Meas B
Cont
CONV
7
Ncont
6
Int B
Cont
CONV
CONV × mbsy
CONV × mbsy
8
Ncont
CONV|mbsy
Figure 10. Integrate/Measure State Diagram
During cont mode, mbsy is not active when CONV toggles.
The non-integrating side is always ready to begin
integrating when the other side finishes its integration.
Consequently, monitoring the current status of CONV is all
that is needed to know the current state. Cont mode
operation corresponds to states 3-6. Two of the states, 3
and 6, only perform an integration (no m/r/az cycle).
mbsy becomes important when operating in the ncont
mode, states 1, 2, 7, and 8. Whenever CONV is toggled
while mbsy is active, the DDC114 will enter or remain in
either ncont state 1 (or 8). After mbsy goes inactive, state
2 (or 7) is entered. This state prepares the appropriate side
for integration. In ncont states, the inputs to the DDC114
are grounded.
One interesting observation from the state diagram is that
the integrations always alternate between sides A and B.
This relationship holds for any CONV pattern and is
independent of the mode. States 2 and 7 insure this
relationship during ncont mode.
When power is first applied to the DDC114, the beginning
state is either 1 or 8, depending on the initial level of CONV.
For CONV held high at power-up, the beginning state is 1.
Conversely, for CONV held low at power-up, the beginning
state is 8. In general, there is a symmetry in the state
diagram between states 1-8, 2-7, 3-6, and 4-5. Inverting
CONV results in the states progressing through their
symmetrical match.