DDC114IRTCT Datasheet, PDF (24/35 Pages) Texas Instruments – Quad Current Input, 20-Bit Analog-To-Digital Converter

DDC114
SBAS255C − JUNE 2004 − REVISED APRIL 2009
RETRIEVAL AFTER CONV TOGGLES
(CONTINUOUS MODE)
For shorter integration times, more time is available if data
retrieval begins after CONV toggles and ends before the
new data is ready. Data retrieval must wait t₂₉ after CONV
toggles before beginning. See Figure 24 for an example of
this. The maximum time available for retrieval is
t₂₇ − t₂₉ – t₂₆ (344.875µs – 10µs – 1.75µs for
CLK = 4MHz), regardless of T_INT. The maximum number
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of DDC114s that can be daisy-chained together (FORMAT
= high) is calculated by Equation 3:
333.125ms
80t_DCLK
(3)
NOTE: 64τ_DCLK is used for FORMAT = low.
For DCLK = 10MHz, the maximum number of DDC114s is
41 (or 52 for FORMAT = low).
CONV
DVALID
DCLK
DOUT
T_INT
t₂₇
t₂₉
…
…
Side A
Data
T_INT
t₂₆
…
…
Side B
Data
T_INT
…
…
Side A
Data
SYMBOL DESCRIPTION
t₂₆
Hold Time that DOUT is Valid Before Falling Edge of DVALID
t₂₇
Cont Mode Data Ready
t₂₉
Data Retrieval Start-Up After Edge of CONV
CLK = 4MHz, CLK_4X = 0
MIN
TYP
MAX
1.75
345.00 ± 0.125
10
CLK = 4.8MHz, CLK_4X = 0
MIN
TYP
MAX
1.458
287.5 ± 0.104
10
UNITS
µs
µs
µs
Figure 24. Readback After CONV Toggles
24