DDC114IRTCT Datasheet, PDF (15/35 Pages) Texas Instruments – Quad Current Input, 20-Bit Analog-To-Digital Converter

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TIMING EXAMPLES
Cont Mode
A few timing diagrams help illustrate the operation of the
state machine. These diagrams are shown in Figure 11
through Figure 19. Table 6 gives generalized timing
specifications in units of CLK periods for CLK_4X = 0. If
CLK_4X = 1, these values increase by a factor of four
because of the internal clock divider. Values (in µs) for
Table 6 can be easily found for a given CLK. For example,
if CLK = 4MHz, then a CLK period = 0.25µs. t₆ in Table 6
would then be 367.50 ± 0.125µs.
Table 6. Timing Specifications Generalized in
CLK Periods
SYMBOL DESCRIPTION
VALUE
(CLK periods with CLK_4X = 0)
t₆
Cont mode m/r/az cycle
1470 ± 0.5
t₇
Cont mode data ready
1380 ± 0.5
t₈
1st ncont mode data ready 1379 ± 1
t₉
2nd ncont mode data ready 1450
t₁₀
Ncont mode m/r/az cycle 2901 ± 1
Figure 11 shows a few integration cycles beginning with
initial power-up for a cont mode example. The top signal
is CONV and is supplied by the user. The next line
indicates the current state in the state diagram. The
following two traces show when integrations and
measurement cycles are underway. The internal signal
DDC114
SBAS255C − JUNE 2004 − REVISED APRIL 2009
mbsy is shown next. Finally, DVALID is given. As
described in the data sheet, DVALID goes active low when
data is ready to be retrieved from the DDC114. It stays low
until DCLK is taken high and then back low by the user. The
text below the DVALID pulse indicates the side of the data
available to be read, and arrows help match the data to the
corresponding integration. The signals illustrated in
Figure 11 through Figure 19 are drawn at approximately
the same scale.
In Figure 11, the first state is ncont state 8. The DDC114
always powers up in the ncont mode. In this case, the first
state is 8 because CONV is initially low. After the first two
states, cont mode operation is reached and the states
begin toggling between 4 and 5. From now on, the input is
being continuously integrated, either on side A or side B.
The time needed for the m/r/az cycle, or t₆, is the same time
that determines the boundary between the cont and ncont
modes described earlier in the Overview section. DVALID
goes low after CONV toggles in time t₇, indicating that data
is ready to be retrieved. As shown in Figure 11, there are
two values for t₆ and t₇. The reason for this is discussed in
the Special Considerations section.
See Figure 12 for the timing diagram of the internal
operations occurring during continuous mode operation.
Table 7 gives the timing specifications in the continuous
mode.
CONV
State 8
7
Integration
Status
m/r/az
Status
mbsy
6
Integrate B
5
Integrate A
m/r/az B
t₆
4
Integrate B
m/r/az A
5
Integrate A
m/r/az B
DVALID
t=0
Power−Up
SYMBOL
t₆
t₇
DESCRIPTION
Cont Mode m/r/az Cycle
Cont Mode Data Ready
t₇
Side B
Da ta
Side A
Data
Side B
Data
VALUE (CLK = 4MHz, CLK_4X = 0)
367.50 ± 0.125µs
345.00 ± 0.125µs
VALUE (CLK = 4.8MHz, CLK_4X = 0)
306.25 ± 0.104µs
287.5 ± 0.104µs
Figure 11. Continuous Mode Timing
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