DDC114IRTCT Datasheet, PDF (12/35 Pages) Texas Instruments – Quad Current Input, 20-Bit Analog-To-Digital Converter

DDC114
SBAS255C − JUNE 2004 − REVISED APRIL 2009
DDC114 Frequency Response
The frequency response of the DDC114 is set by the front
end integrators and is that of a traditional continuous time
integrator, as shown in Figure 7. By adjusting T_INT, the user
can change the 3dB bandwidth and the location of the
notches in the response. The frequency response of the
∆Σ converter that follows the front end integrator is of no
consequence because the converter samples a held
signal from the integrators. That is, the input to the ∆Σ
converter is always a DC signal. Since the output of the
front end integrators are sampled, aliasing can occur.
Whenever the frequency of the input signal exceeds
one-half of the sampling rate, the signal will fold back down
to lower frequencies.
0
−10
−20
−30
−40
−50
0.1
T_INT
1
T_INT
10
T_INT
100
T_INT
Frequency
Figure 7. Frequency Response of the DDC114
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Test Mode
When Test Mode is used, the inputs (IN1, IN2, IN3, and
IN4) are disconnected from the DDC114 integrators to
enable the user to measure a zero input signal regardless
of the current supplied to the inputs. In addition, packets of
charge can be transferred to the integrators in 11pC
intervals to measure non-zero values. The test mode
works with both the continuous and non-continuous
modes. The timing diagram for the test mode is shown in
Figure 8 with the timing specifications given in Table 2.
To enter Test Mode, hold TEST high while CONV
transitions. If TEST is held high during the entire
integration period, the integrators measure a zero value.
This mode can be used to help debug a design or perform
diagnostic tests. To apply packets of charge during Test
Mode, simply strobe TEST low then high before the next
CONV transition. Each rising edge of TEST causes
approximately 11pC of charge to be transferred to the
integrators. This charge transfer is independent of the
integration time. Data retrieval during Test Mode is
identical to normal operation. To exit Test Mode, take
TEST low and allow several cycles after exiting before
using the data.
Test Mode Disabled
Action
Integrate B Integrate A
Test Mode Enabled: Inputs Disconnected
0pC into B 11pC into A 22pC into B 33pC into A
Test Mode Disabled
Integrate B Integrate A
CONV
TEST
t₄
t₆
t₂
t₁
t₃
t₅
t₄
SYMBOL
t₁
t₂
t₃
t₄
t₅
t₆
12
Figure 8. Timing Diagram of the Test Mode of the DDC114
Table 2. Timing for the DDC114 in the Test Mode
DESCRIPTION
MIN
TYP
Setup Time for Test Mode Enable
100
Setup Time for Test Mode Disable
100
Hold Time for Test Mode Enable
100
From Rising Edge of TEST to the Edge of CONV while Test Mode
Enabled
1
Falling Edge to Rising Edge of TEST
1
Rising Edge to Falling Edge of TEST
1
MAX
UNITS
ns
ns
ns
µs
µs
µs