DDC114IRTCT Datasheet, PDF (17/35 Pages) Texas Instruments – Quad Current Input, 20-Bit Analog-To-Digital Converter

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Ncont Mode
Non-continuous (ncont) mode of operation is intended for
ranges 1 to 7. It is not recommended to use Range 0 when
operating in non-continuous mode. Figure 13 illustrates
operation in ncont mode. The integrations come in pairs
(that is, sides A/B or sides B/A) followed by a time during
which no integrations occur. During that time, the previous
integrations are being measured, reset and auto-zeroed.
Before the DDC114 can advance to states 3 or 6, both
sides A and B must be finished with the m/r/az cycle, which
takes time t₁₀. When the m/r/az cycles are completed, time
t₁₁ is needed to prepare the next side for integration. This
time is required for ncont mode because the m/r/az cycle
of ncont mode is slightly different from that of cont mode.
After the first integration ends, DVALID goes low in time t₈.
DDC114
SBAS255C − JUNE 2004 − REVISED APRIL 2009
This time is the same as in cont mode. The second data will
be ready in time t₉ after the first data is ready. One result
of the naming convention used in this data sheet is that
when the DDC114 is operating in ncont mode, it passes
through both ncont mode states and cont mode states. For
example, in Figure 13, the state pattern is 3, 4, 1, 2, 3, 4,
1, 2, 3, 4 ... where 3 and 4 are cont mode states. Ncont
mode, by definition, means that for some portion of the
time, neither side A nor B is integrating. States that perform
an integration are labeled cont mode states, while those
that do not are called ncont mode states. Since
integrations are performed in ncont mode, just not
continuously, some cont mode states must be used in an
ncont mode state pattern.
CONV
State
Integration
Status
m/r/az
Status
mbsy
DVALID
SYMBOL
t₈
t₉
t₁₀
t₁₁
3
4
1
Int A Int B
23
4
t₁₁
Int A Int B
m/r/az A
m/r/az B
t₁₀
m/r/az A
1
2
m/r/az B
t₉
t₈
Side A
Data
Side B
Data
Side A
Data
Side B
Data
DESCRIPTION
1st ncont Mode Data Ready
2nd ncont Mode Data Ready
ncont Mode m/r/az Cycle
Prepare Side for Integration
VALUE (CLK = 4MHz, CLK_4X = 0)
344.75 ± 0.25µs
362.5µs
725.25 ± 0.25µs
≥ 18µs
VALUE (CLK = 4.8MHz, CLK_4X = 0)
287.292 ± 0.208µs
302.083µs
604.375 ± 0.208µs
≥ 15µs
Figure 13. Non-Continuous Mode Timing
17