DDC114IRTCT Datasheet, PDF (23/35 Pages) Texas Instruments – Quad Current Input, 20-Bit Analog-To-Digital Converter

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RETRIEVAL BEFORE CONV TOGGLES
(CONTINUOUS MODE)
Data retrieval before CONV toggles is the most
straightforward method. Data retrieval begins soon after
DVALID goes low and finishes before CONV toggles; as
shown in Figure 23. For best performance, data retrieval
must stop t₂₈ before CONV toggles. This method is most
appropriate for longer integration times. The maximum
time available for readback is T_INT – t₂₇ – t₂₈. For DCLK =
10MHz and CLK = 4MHz, the maximum number of
DDC114s that can be daisy-chained together (FORMAT =
high) is calculated by Equation 1:
T_INT * 355.125ms
80t_DCLK
(1)
DDC114
SBAS255C − JUNE 2004 − REVISED APRIL 2009
NOTE: 64τ_DCLK is used for FORMAT = low.
where τ_DCLK is the period of the data clock. For example,
if T_INT = 1000µs and DCLK = 10MHz, the maximum
number of DDC114s (FORMAT = high) is shown in
Equation 2:
1000ms * 355.125ms
(80)(100ns)
+
80.60
³
80
DDC114s
(2)
(or 100 for FORMAT = low).
CONV
DVALID
DCLK
DOUT
T_INT
t₂₇
t₂₈
…
…
Side B
Data
T_INT
…
…
Side A
Data
SYMBOL DESCRIPTION
t₂₇
Cont Mode Data Ready
t₂₈
Data Retrieval Shutdown Before Edge of CONV
CLK = 4MHz, CLK_4X = 0
MIN
TYP
MAX
345.00 ± 0.125
10
CLK = 4.8MHz, CLK_4X = 0
MIN
TYP
MAX
287.5 ± 0.104
10
UNITS
µs
µs
Figure 23. Readback Before CONV Toggles
23