TMS320TCI6602 Datasheet, PDF (79/201 Pages) Texas Instruments – Multicore Fixed and Floating-Point Digital Signal Processor

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TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 3-18 Timer Output Selection Field Description (TOUTPSEL)
Bit
31-10
9-5
Field
Reserved
TOUTPSEL1
4-0
TOUTPSEL0
End of Table 3-18
Description
Reserved
Output select for TIMO1
00000: TOUTL0
00001: TOUTH0
00010: TOUTL1
00011: TOUTH1
Output select for TIMO0
00000: TOUTL0
00001: TOUTH0
00010: TOUTL1
00011: TOUTH1
00100: TOUTL2
00101: TOUTH2
00110: TOUTL3
00111: TOUTH3
01000 to 11111: Reserved
00100: TOUTL2
00101: TOUTH2
00110: TOUTL3
00111: TOUTH3
01000 to 11111: Reserved
3.3.18 Reset Mux (RSTMUXx) Register
The software controls the Reset Mux block through the reset multiplex registers using RSTMUX0 through
RSTMUX1 for each of the two CorePacs on the TCI6602. These registers are located in Bootcfg memory space. The
Timer Output Selection Register is shown in Figure 3-17 and described in Table 3-19.
Figure 3-17 Reset Mux Register RSTMUXx
31
10
9
8
7
5
Reserved
EVTSTATCLR
Reserved
DELAY
R, +0000 0000 0000 0000 0000 00
RC, +0
R, +0
RW, +100
Legend: R = Read only; RW = Read/Write; -n = value after reset; RC = Read only and write 1 to clear
4
EVTSTAT
R, +0
3
1
OMODE
RW, +000
0
LOCK
RW, +0
Table 3-19 Reset Mux Register Field Descriptions (Part 1 of 2)
Bit Field
31-10 Reserved
9 EVTSTATCLR
8 Reserved
7-5 DELAY
4 EVTSTAT
Description
Reserved
Clear event status.
0 = Writing O had no effect
1 = Writing 1 to this bit clears the EVTSTAT bit
Reserved
Delay cycles between NMI & Local reset.
000b = 256 DSP/6 cycles delay between NMI & local reset, when OMODE = 100b
001b = 512 DSP/6 cycles delay between NMI & local reset, when OMODE=100b
010b = 1024 DSP/6 cycles delay between NMI & local reset, when OMODE=100b
011b = 2048 DSP/6 cycles delay between NMI & local reset, when OMODE=100b
100b = 4096 DSP/6 cycles delay between NMI & local reset, when OMODE=100b (Default)
101b = 8192 DSP/6 cycles delay between NMI & local reset, when OMODE=100b
110b = 16384 DSP/6 cycles delay between NMI & local reset, when OMODE=100b
111b = 32768 DSP/6 cycles delay between NMI & local reset, when OMODE=100b
Event status.
0 = No event received (Default)
1 = WD timer event received by Reset Mux block
Copyright 2011 Texas Instruments Incorporated
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