TMS320TCI6602 Datasheet, PDF (71/201 Pages) Texas Instruments – Multicore Fixed and Floating-Point Digital Signal Processor

TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
www.ti.com
SPRS782A—August 2011
3.3.5 LRESETNMI PIN Status (LRSTNMIPINSTAT) Register
The LRSTNMIPINSTAT Register is created in Boot Configuration to latch the status of LRESET and NMI based on
CORESEL. The LRESETNMI PIN Status Register is shown in Figure 3-4 and described in Table 3-6 .
Figure 3-4 LRESETNMI PIN Status Register (LRSTNMIPINSTAT)
31
18
17
16
15
2
1
0
Reserved
NMI1 NMI0
Reserved
LR1
LR0
R, +0000 0000
R-0
R-0
R, +0000 0000
R-0
R-0
Legend: R = Read only; -n = value after reset;
Table 3-6
LRESETNMI PIN Status Register (LRSTNMIPINSTAT) Field Descriptions
Bit
Field
31-18 Reserved
17 NMI1
16 NMI0
15-2 Reserved
1 LR1
0 LR0
End of Table 3-6
Description
Reserved
CorePac 1 in NMI
CorePac 0 in NMI
Reserved
CorePac 1 in Local Reset
CorePac 0 in Local Reset
3.3.6 LRESETNMI PIN Status Clear (LRSTNMIPINSTAT_CLR) Register
The LRSTNMIPINSTAT_CLR Register is used to clear the status of LRESET and NMI based on CORESEL. The
LRESETNMI PIN Status Clear Register is shown in Figure 3-5 and described in Table 3-7.
Figure 3-5 LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR)
31
18
17
16
15
2
1
0
Reserved
NMI1 NMI0
Reserved
LR1
LR0
R, +0000 0000
WC,+0 WC,+0
R, +0000 0000
WC,+0 WC,+0
Legend: R = Read only; -n = value after reset; WC = Write 1 to Clear
Table 3-7
LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR) Field Descriptions
Bit
Field
31-18 Reserved
17 NMI1
16 NMI0
15-2 Reserved
1 LR1
0 LR0
End of Table 3-7
Description
Reserved
CorePac 1 in NMI Clear
CorePac 0 in NMI Clear
Reserved
CorePac 1 in Local Reset Clear
CorePac 0 in Local Reset Clear
3.3.7 Reset Status (RESET_STAT) Register
The reset status register (RESET_STAT) captures the status of Local reset (LRx) for each of the cores and also the
global device reset (GR). Software can use this information to take different device initialization steps, if desired.
• In case of Local reset: The LRx bits are written as 1 and GR bit is written as 0 only when the CorePac receives
an local reset without receiving a global reset.
Copyright 2011 Texas Instruments Incorporated
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